Dear SI professionals, Could anyone give some inputs for *backplane interconncetion* (chip on blade-to-backplane-to-chip on blade)? I want to hear especially your opinion to start the project I am engaged in right now. 1. What is the state of the art technolgy for backplane interconnection? 2. Are signal impairment compensation technolgy, such as Pre-emphasis, equalizer etc, are practically well applied in real design world? Or is it just a sales pitch? (3G, 6G, 10G, 40G,..) 3. I know some designers suppress these features and stick to classical external termination method because of, FOR EXAMPLE, the issues like SSN, power consumption etc. Do you have Other issues? 4. For technolgy I see the issues for latency (few hundreds nanosec for FEC..) and power consumption (total bay power constraints...). Any opinion on this? 5. Would temperature mean to SI for high-speed backplane? If it does, what sensitity? 6. Want to discuss for today's and two years after technolgy, in terms of speed (bit/sec) associated to the specific technolgy (mostly serial IO technolgy, I presume). I am having trouble to get these kind of infos because most vendors are so conservative for their IP issues. Best Regards, Kihong Joshua Kim SI Consultant, Photonics and Electronics ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu