I like stackup A, but have the following question. If I make the spacings between layers 3 & 4 and between layers 5 & 6 big, this will affect the trace impedance on layer 3 and layer 6 respectively. Therefore, I'm thinking about keeping these spacings small, but increasing the spacing between layers 4 and 5 (between +5V and +12 planes) to meet the required PCB thickness. Are there any disadvantages? 1) Signals small space 2) GND small space 3) Signals small space 4) +5V BIG space 5) +12V small space 6) Signals small space 7) GND small space 8) Signals _________________________________________________________________ FREE pop-up blocking with the new MSN Toolbar ? get it now! http://toolbar.msn.click-url.com/go/onm00200415ave/direct/01/ ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu