[SI-LIST] Re: 8-layer PCB Stackup - Follow Up
- From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
- To: <kevin98146@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 25 Jun 2004 08:18:26 -0600
That's where you would normally pad, in the plane of symmetry between the
board "halves". The loop inductance increases if you have layers 1 and 3
referencing +12 (or 6&8 referencing +5). If you are doing a standard 0.062
board, and are running edge-rates at around 1 ns, clocking at 100MHz, there
shouldn't be any problem. If you are going significantly faster, it's a
whole 'nother ball game, and you need to get a high-speed consultant.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Kevin Khuu
Sent: Thursday, June 24, 2004 4:05 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] 8-layer PCB Stackup - Follow Up
I like stackup A, but have the following question.
If I make the spacings between layers 3 & 4 and between layers 5 & 6 big,
this will affect the trace impedance on layer 3 and layer 6 respectively.
Therefore, I'm thinking about keeping these spacings small, but increasing
the spacing between layers 4 and 5 (between +5V and +12 planes) to meet the
required PCB thickness. Are there any disadvantages?
1) Signals
small space
2) GND
small space
3) Signals
small space
4) +5V
BIG space
5) +12V
small space
6) Signals
small space
7) GND
small space
8) Signals
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