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- » [SI-LIST] Passivity Enforcement Matlab Code -
- » [SI-LIST] Queries related to XTK -
- » [SI-LIST] Re: Queries related to XTK -
- » [SI-LIST] Re: IBIS question!! -
- » [SI-LIST] 6-layer vs 7-layer PCB Stackup -
- » [SI-LIST] Agenda - IBIS Open Forum Summit, June 8, 2004 -
- » [SI-LIST] Re: 6-layer vs 7-layer PCB Stackup -
- » [SI-LIST] Re: 6-layer vs 7-layer PCB Stackup -
- » [SI-LIST] Re: 6-layer vs 7-layer PCB Stackup -
- » [SI-LIST] Re: 6-layer vs 7-layer PCB Stackup -
- » [SI-LIST] Re: 6-layer vs 7-layer PCB Stackup -
- » [SI-LIST] Re: 6-layer vs 7-layer PCB Stackup -
- » [SI-LIST] off topic a little... power cable -
- » [SI-LIST] Re: IBIS question!! -
- » [SI-LIST] Re: off topic a little... power cable -
- » [SI-LIST] Re: Queries related to XTK -
- » [SI-LIST] Re: IBIS question!! -
- » [SI-LIST] Power plane resonace for multi-plane issues -
- » [SI-LIST] =?big5?q?=A6^=ABH=A1G?= Power plane resonace for multi-plane issues -
- » [SI-LIST] Re: Power plane resonace for multi-plane issues -
- » [SI-LIST] Re: Power plane resonace for multi-plane issues -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] Re: Queries related to XTK -
- » [SI-LIST] Test equipment recommendations? -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] accuracy of industry spice tools -
- » [SI-LIST] Re: accuracy of industry spice tools -
- » [SI-LIST] unsubscribe -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] Re: Power plane resonace for multi-plane issues -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] Re: IBIS question!! -
- » [SI-LIST] DAC SI and PI Technical Material -
- » [SI-LIST] Didn't really unsubscribe!! -
- » [SI-LIST] Re: IBIS question!! -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] SI-Wiki additions -
- » [SI-LIST] Re: 50 ohm and 130 ohm on the same board -
- » [SI-LIST] System tests misapplied to devices and modules -
- » [SI-LIST] pre-emphais buffer in ADS -
- » [SI-LIST] near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: Welcome to list 'si-list' -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] IEEE CPMT Society Phoenix Chapter - June 29 meeting announcement -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Crystal oscillator simulation in time domain by Pspice -
- » [SI-LIST] Re: Crystal oscillator simulation in time domain by Pspice -
- » [SI-LIST] Re¡G Re: Crystal oscillator simulationin time domain by Pspice -
- » [SI-LIST] Re: Crystal oscillator simulation in time domain by Pspice -
- » [SI-LIST] hyperlynx or spectraquest -
- » [SI-LIST] Re: Crystal oscillator simulation in time domain by Pspice -
- » [SI-LIST] hyperlynx or spectraquest -
- » [SI-LIST] Re: si-list Digest V4 #240 -
- » [SI-LIST] Re: near and far end crosstalk in frequency domain -
- » [SI-LIST] Re: Crystal oscillator simulation in time domain by Pspice -
- » [SI-LIST] Re: Crystal oscillator simulation in time domain by Pspice -
- » [SI-LIST] Re: Crystal oscillator simulation in time domain byPspice -
- » [SI-LIST] A question about ESD protection of high speed I/O IC -
- » [SI-LIST] Job openning. -
- » [SI-LIST] Capturing the effects of impedance variation due to plane splits -
- » [SI-LIST] Which Field Solver Is Based on MoM -
- » [SI-LIST] si-list High speed part -
- » [SI-LIST] Re: Which Field Solver Is Based on MoM -
- » [SI-LIST] Skin effect in ADS -
- » [SI-LIST] Re: Skin effect in ADS -
- » [SI-LIST] PCB or Package LCR measurement -
- » [SI-LIST] What happen to FR4 if exposed under strong E field or H field? -
- » [SI-LIST] Re: What happen to FR4 if exposed under strong E field or H field? -
- » [SI-LIST] Re: What happen to FR4 if exposed under strong E field or H field? -
- » [SI-LIST] si-list Digest V4 #245 -
- » [SI-LIST] Re: Skin effect in ADS -
- » [SI-LIST] si-list Digest V4 #246 -
- » [SI-LIST] IBIS services -
- » [SI-LIST] Re: What happen to FR4 if exposed under strong E fieldor H field? -
- » [SI-LIST] Wavecrest cart -
- » [SI-LIST] Wander in clock -
- » [SI-LIST] Re: Wander in clock -
- » [SI-LIST] Re: Wander in clock -
- » [SI-LIST] Definition of "Data Input Pulse Width" for DDRII -
- » [SI-LIST] Hyperlynx -
- » [SI-LIST] Re: Hyperlynx -
- » [SI-LIST] Engineer opening at IDI in Kansas -
- » [SI-LIST] Fw: PCB Copper Heatsink -
- » [SI-LIST] Re: Fw: PCB Copper Heatsink -
- » [SI-LIST] s2ibis2 extreme currents -
- » [SI-LIST] Re: [BULK] - s2ibis2 extreme currents -
- » [SI-LIST] Re: [BULK] - s2ibis2 extreme currents -
- » [SI-LIST] Re: Fw: PCB Copper Heatsink -
- » [SI-LIST] Spread Spectrum Clock Multiplier -
- » [SI-LIST] SPICE books -
- » [SI-LIST] Young's modulus and Poisson ratio for a PCB -
- » [SI-LIST] Re: Spread Spectrum Clock Multiplier -
- » [SI-LIST] SPICE Model for OSC -
- » [SI-LIST] Chassis Ground connected to Signal Ground -
- » [SI-LIST] resend: s2ibis2 extreme currents -
- » [SI-LIST] Terminated Bidi model -
- » [SI-LIST] Re: Terminated Bidi model -
- » [SI-LIST] Re: Terminated Bidi model -
- » [SI-LIST] Re: resend: s2ibis2 extreme currents -
- » [SI-LIST] Re: resend: s2ibis2 extreme currents -
- » [SI-LIST] 回复:Chassis Ground connected to Signal Ground -
- » [SI-LIST] Re: Chassis Ground connected to Signal Ground -
- » [SI-LIST] RMCEMC SI presentation notice -
- » [SI-LIST] Re: SPICE books -
- » [SI-LIST] diff pair termination -
- » [SI-LIST] Re: diff pair termination -
- » [SI-LIST] Time step for plotting eye patterns -
- » [SI-LIST] balance and un-balance -
- » [SI-LIST] Partial Inductance Software -
- » [SI-LIST] Re: CST Microwave to Cadence Interface -
- » [SI-LIST] Re: Partial Inductance Software -
- » [SI-LIST] Time Domain Network Analysis and TDR White Papers -
- » [SI-LIST] Re: Partial Inductance Software -
- » [SI-LIST] Re: Partial Inductance Software -
- » [SI-LIST] IBIS Tristate Buffer for Simulation -
- » [SI-LIST] Re: IBIS Tristate Buffer for Simulation -
- » [SI-LIST] 8-layer PCB stackup -
- » [SI-LIST] Re: 8-layer PCB stackup -
- » [SI-LIST] Re: 8-layer PCB stackup -
- » [SI-LIST] Re: 8-layer PCB stackup -
- » [SI-LIST] SI Engineer available in Silicon Valley -
- » [SI-LIST] Re: diff pair termination -
- » [SI-LIST] Material Properties -
- » [SI-LIST] Re: 8-layer PCB stackup -
- » [SI-LIST] 4 Layer Stackups -
- » [SI-LIST] Re: Material Properties -
- » [SI-LIST] 8-layer PCB Stackup - Follow Up -
- » [SI-LIST] Re: 4 Layer Stackups -
- » [SI-LIST] Re: 4 Layer Stackups -
- » [SI-LIST] Current and Trace Width -
- » [SI-LIST] Re: Material Properties -
- » [SI-LIST] Re: 8-layer PCB stackup -
- » [SI-LIST] Re: Current and Trace Width -
- » [SI-LIST] Substrates -
- » [SI-LIST] TI TMS320VC5416 IBIS model -
- » [SI-LIST] Re: Material Properties -
- » [SI-LIST] Re: 4 Layer Stackups -
- » [SI-LIST] Re: 8-layer PCB Stackup - Follow Up -
- » [SI-LIST] Re: SI Engineer available in Silicon Valley -
- » [SI-LIST] Re: Substrates -
- » [SI-LIST] Re: SI Engineer available in Silicon Valley -
- » [SI-LIST] Re: SI Engineer available in Silicon Valley -
- » [SI-LIST] Crosstalk Noise Amplitude -
- » [SI-LIST] Re: Crosstalk Noise Amplitude -
- » [SI-LIST] Re: Crosstalk Noise Amplitude -
- » [SI-LIST] Fw: About the spacing between GND pad and PCIE traces -
- » [SI-LIST] Re: Fw: About the spacing between GND pad and PCIE traces -
- » [SI-LIST] Re: Fw: About the spacing between GND pad and PCIE traces -
- » [SI-LIST] Jay Diepenbrock is out of the office. -
- » [SI-LIST] (probably naive) FPGA PDS questions -
- » [SI-LIST] Re: (probably naive) FPGA PDS questions -
- » [SI-LIST] Re: (probably naive) FPGA PDS questions -
- » [SI-LIST] Re: Crosstalk Noise Amplitude -
- » [SI-LIST] RMCEMC June meeting reminder and Bonus gift -
- » [SI-LIST] Re: (probably naive) FPGA PDS questions -
- » [SI-LIST] 1995 original paper -
- » [SI-LIST] Re: 1995 original paper -
- » [SI-LIST] diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: diff pair signal -
- » [SI-LIST] Re: si-list Digest V4 #261 -
- » [SI-LIST] Re: Digest Number 1144 -