Vincenzo, you are perfactly alirght when you mention the space left for pads. but you did not talk about the tracks escaping between vias. but when i place vias a matrix form, there is only 31.496 mil distance between the centers of adjacent via pads. keeping via pad of 20 mil there is only 11.496 mil space left between the pads of adjacent vias. Now if i use 5/5 routing this means i need 5+5+5 = 15 mils total space for routing atleast one track between the pads of adjacent vias, which in our case is only 11.496. Even 4/4 routing scheme does not allow me to route/escape one track between the pads of adjacent vias. I am attaching the rough diagram for reference. What you say in this regard? Also please let me know the links/documents reffering to the design of BGAs with 0.8 mm pitch. Thanks Tayyab -----Original Message----- From: Vincenzo Kreft-Kerekes [mailto:vincenzo@xxxxxxxxxxxxxx] Sent: Friday, December 26, 2003 10:19 PM To: tayyab@xxxxxxxxxxxxxx Subject: [SI-LIST] Re: 0.8mm BGA routing Tayyab, You place escape vias diagonally in the 0.8 mm raster which means you have 0.8 * sqrt(2) = 1.13 mm (44.5 mil) to work with. If you're using a 20 mil via pad and have an etch capable of resolving 5 mil spaces between copper structures then you need a 30 mil zone around your via hole center (for pad and clearance) which leaves 44.5 - 30 = 14.5 mil as pad diameter for the ball. As was already mentioned, Xilinx has escape diagrams for most if not all of their packages so you can look at what we're talking about, Altera also has a good application note on this topic and both have recommended values for the via and etch parameters in these documents. Regards, Vincenzo -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Tayyab Jamil Sent: Thursday, December 25, 2003 11:35 PM To: Stephen Chavez Cc: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: 0.8mm BGA routing Hi, I could not understand your scheme, for me it is not possible what you suggest as 0.8 mm pitch means there is only about 31 mil distance between via pads of adjacent pins. 24 mil pad of via leaves only around 7.xx mils space in between. If we use 5 mil trace this leaves only around 2.xx mils in total on both sides of the trace, means 1.xx mil clearence on each side of trace. What i was thinking of is 18mil via pad and 8mil via hole finished, and 4mil trace and 4mil clearnce. This allows one trace to be escaped between adjacent pades. Any suggestions about this. Please let me know if I am wrong. Regards Tayyab -- Binary/unsupported file stripped by Ecartis -- -- Type: application/octet-stream -- File: Preview PCB1.pdf ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu