[PCB_FORUM] Re: Trying to find a specific drill size (via to via)
- From: "westfeldt" <westfeldt_nbcd@xxxxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Tue, 15 Jun 2004 18:04:46 -0600
microvias 1-2 and 7-8 will come out as drc if you don't have control over bb
stagger, which is a feature not available in PCB Design Studio. Even though
the control is not there, the software(at least in 14.2) says there is a
stagger error because there is a built-in default of 5 mils minimum spacing.
So 1-2 and 7-8 vias colocated in xy space will get you a drc. I think this
was true in all PCB Design Studio v13 and v14, don't know about v15.
> -----Original Message-----
> From: Gene Carman [mailto:gcarman@xxxxxxxxxxxxxxx]
> Sent: Tuesday, June 15, 2004 5:04 PM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Trying to find a specific drill size (via to
> via)
>
>
> I ran into a bit of a issue with via to via... my DRC report
> showed vias on top of vias that were actually quite separated...
> vertically. I had 1-2 micro vias above 7-8 microvias and these
> came out as errors on the DRC report. That strikes me as a problem.
>
> -----Original Message-----
> From: Mitch S. Morey [mailto:cadpro2k@xxxxxxxxxx]
> Sent: Tuesday, June 15, 2004 3:51 PM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Trying to find a specific drill size
>
>
> Been reading the thread, and I still don't know why you need to create the
> file. As many boards as I've done, I've never created it. Never needed
> too. When you run DBCheck routine, does it show you duplicate hits on the
> drill in question? It will if they are vias. What I do do now (since we
> were hit with redundant drills) is create a simple script that changes my
> constraints to look at 'same net' vias and will report if they less than 5
> mils apart. Then I simply turn on all the layer DRCs and select them as
> 'info' and save the file as a text file. I search that for 'via to via'
> spacings, and shows me ANY violations. Simple, quick, 'almost perfect'.
>
> Did I miss something?
>
> Good day.
>
> Mitch
>
> > Thanks to all for your helpful info. Unless I missed something I still
> > can't believe that Allegro can't generate this nc_tools.txt file
> > automatically rather than the designer having to do this every time and
> > on every respin.
> >
> > Tony Stanislao, Senior PCB Design Engineer
> > Pannaway Technologies | v: 603.766.5129| e: stanislao_t@xxxxxxxxxxxx
> > =========================================
>
>
>
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