All,
I am enclosing a presentation that cleans up the definition of [Die Supply
Pads], defines clear rules on the usage of signal_name and bus_labels, and
outlines a simple implementation of these rules.
I expect that one can create absurd cases which will fail these rules and
pass the existing IBIS parser, but I consider these examples to truly be
absurd, and something that I think all of the EDA companies will not want
to support.
I have requested that Bob represent the following simple example using
[Pin Pad Map]:
A component has 100 VDD pins (P1, P2, .P100) and all of these VDD pins
have the same bus_label (VDD).
The component has 5 VDD die pads (D1, D2, D3, D4, D5), and all of these
VDD die pads have the same bus_label.
Walter
Walter Katz
<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx
Phone 303.449-2308
Mobile 303.335-6156
Attachment:
[Die Supply Pads].pptx
Description: MS-Powerpoint 2007 presentation
