Bob,
So the following:
[Pin Pad Map] pad_name
P1 D1
P21 D2
P41 D3
P61 D4
P81 D5 | 5 lines
[End Pin Pad Map]
Requires the tool to take the line:
P1 D1
Search the pin list for P1 to find that it is VDD.
Why do we need this level of indirection?
Why not eliminate the useless indirection with the following Die Supply
Pad record?
D1 VDD
Can you give any logical answers to these two simple questions?
Walter
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Bob Ross
Sent: Monday, January 4, 2016 7:34 PM
To: 'IBIS-Interconnect' <ibis-interconn@xxxxxxxxxxxxx>
Subject: [ibis-interconn] Re: [Die Supply Pads]
Walter,
I already responded to your question with text. Here it is
with some expanded content:
[Pin Pad Map] pad_name
P1 D1
P2 D1
| .
P19 D1
P20 D2
| ..
P39 D2
| .
| .
P100 D5 | 100 lines
[End Pin Pad Map]
The simplified version where all of the pin_names do
not have to be listed would just have 5 lines, for example,:
[Pin Pad Map] pad_name
P1 D1
P21 D2
P41 D3
P61 D4
P81 D5 | 5 lines
[End Pin Pad Map]
Bob
From: ibis-interconn-bounce@xxxxxxxxxxxxx
<mailto:ibis-interconn-bounce@xxxxxxxxxxxxx>
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Monday, January 04, 2016 3:47 PM
To: IBIS-Interconnect
Subject: [ibis-interconn] Re: [Die Supply Pads]
Bob,
The point of this example is that 5 die pads are needed. The package PDN
model will have 105 terminals, 100 pin terminals and 5 die pad terminals.
I did not include the I/O in the example, but assume 50 I/O with VDD
Puref. The on-die PDN model will have 55 terminals, 50 for the I/O and 5
for the die pads.
The actual PDN network on the package is a power plane with 100 pin
connections and 5 die pad connections. All 100 Pins connect to all 5 pads
in a complex way. The actual PDN on the die is also a power plane with 50
connections to I/O buffer puref terminals and 5 connections to die pad
terminals. All 50 I/O buffers connect to all 5 pads in a complex way.
Please generate the [Pin Pad Map] data for this example.
The [Die Supply Pads] for this case is:
[Die Supply Pads]
D1 VDD
D2 VDD
D3 VDD
D4 VDD
D5 VDD
[End Die Supply Pads]
This is the simplest test but real test case for a power delivery network.
The number 5 for the number of VDD die pads is arbitrary, it could easily
be 50, 100, or 200, but I left it small to make it easy to generate the
actual die pad data.
Walter
From: ibis-interconn-bounce@xxxxxxxxxxxxx
<mailto:ibis-interconn-bounce@xxxxxxxxxxxxx>
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Bob Ross
Sent: Monday, January 4, 2016 6:28 PM
To: 'IBIS-Interconnect' <ibis-interconn@xxxxxxxxxxxxx
<mailto:ibis-interconn@xxxxxxxxxxxxx> >
Subject: [ibis-interconn] Re: [Die Supply Pads]
All,
Since Walter and I dealt with some of these cases in private e-mail, this
is a public
response to the Interconnect group to the questions.
A component has 100 VDD pins (P1, P2, ... P100) and all of these VDD pins
have the same
bus_label (VDD).
If pad_names are not needed, just use the [Pin] list for signal_names for
P1-P100, and use Bus_label_signal_name (or the proposed
Signal_names_are_bus_labels) to avoid the extra
100 lines in [Pin Mapping]. 100 lines are still needed for under [Pin Pad
Map] for P1-P100
to define and associate the 5 pad_names, versus 5 lines with [Die Supply
Pads].
----
The component has 5 VDD die pads (D1, D2, D3, D4, D5), and all of these
VDD die pads have
the same bus_label.
Simplification in [Pin Mapping] is achieved when the bus_label are the
same as the
signal_name. Otherwise, pins P1-P100 need to be listed in [Pin Mapping].
Similarly,
100 lines need to be listed for [Pin Pad Map] for each pin to document the
5 pad_names.
Some proposed new rules for [Die Supply Pads] can eliminate the need for
extra lines
in [Pin Mapping].
----
However, we could change the [Pin Pad Map] rule to state that only a
subset of pins
are required that defines each of the unique pad_names.
So with this revised rule:
[Pin Pad Map] pad_name
P1 D1
P21 D2
P41 D2
P61 D4
P81 D5
The required [Pin] keyword already defines all the pin_names, and
the IBIS-ISS file or Touchstone file defines what is really
electrically connected to the defined terminal qualifiers.
-----
Regarding the attached presentation, and per our private e-mail,
I disagree on slide 6, bullets 3 and 4. There are real and legal
IBIS model counter-examples. A reason for [Pulldown Reference]
and [GND Clamp Reference] is to document the [Pulldown] and [GND
Clamp] table reference voltages to be non-0 (in other words,
they could be POWER pins with VSSX signal_names. Similarly
for [Pullup Reference] and [POWER Clamp Reference] could be 0 V
(as with ECL) with corresponding GND model_name terminal VSS.
So [Pin Mapping] labels should not have the stated restrictions.
Bob
From: ibis-interconn-bounce@xxxxxxxxxxxxx
<mailto:ibis-interconn-bounce@xxxxxxxxxxxxx>
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Monday, January 04, 2016 1:03 PM
To: 'IBIS-Interconnect'
Subject: [ibis-interconn] [Die Supply Pads]
All,
I am enclosing a presentation that cleans up the definition of [Die Supply
Pads], defines clear rules on the usage of signal_name and bus_labels, and
outlines a simple implementation of these rules.
I expect that one can create absurd cases which will fail these rules and
pass the existing IBIS parser, but I consider these examples to truly be
absurd, and something that I think all of the EDA companies will not want
to support.
I have requested that Bob represent the following simple example using
[Pin Pad Map]:
A component has 100 VDD pins (P1, P2, .P100) and all of these VDD pins
have the same bus_label (VDD).
The component has 5 VDD die pads (D1, D2, D3, D4, D5), and all of these
VDD die pads have the same bus_label.
Walter
Walter Katz
<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx
Phone 303.449-2308
Mobile 303.335-6156
