All,
Since Walter and I dealt with some of these cases in private e-mail, this is
a public
response to the Interconnect group to the questions.
A component has 100 VDD pins (P1, P2, ... P100) and all of these VDD pins
have the same
bus_label (VDD).
If pad_names are not needed, just use the [Pin] list for signal_names for
P1-P100, and use Bus_label_signal_name (or the proposed
Signal_names_are_bus_labels) to avoid the extra
100 lines in [Pin Mapping]. 100 lines are still needed for under [Pin Pad
Map] for P1-P100
to define and associate the 5 pad_names, versus 5 lines with [Die Supply
Pads].
----
The component has 5 VDD die pads (D1, D2, D3, D4, D5), and all of these VDD
die pads have
the same bus_label.
Simplification in [Pin Mapping] is achieved when the bus_label are the same
as the
signal_name. Otherwise, pins P1-P100 need to be listed in [Pin Mapping].
Similarly,
100 lines need to be listed for [Pin Pad Map] for each pin to document the 5
pad_names.
Some proposed new rules for [Die Supply Pads] can eliminate the need for
extra lines
in [Pin Mapping].
----
However, we could change the [Pin Pad Map] rule to state that only a subset
of pins
are required that defines each of the unique pad_names.
So with this revised rule:
[Pin Pad Map] pad_name
P1 D1
P21 D2
P41 D2
P61 D4
P81 D5
The required [Pin] keyword already defines all the pin_names, and
the IBIS-ISS file or Touchstone file defines what is really
electrically connected to the defined terminal qualifiers.
-----
Regarding the attached presentation, and per our private e-mail,
I disagree on slide 6, bullets 3 and 4. There are real and legal
IBIS model counter-examples. A reason for [Pulldown Reference]
and [GND Clamp Reference] is to document the [Pulldown] and [GND
Clamp] table reference voltages to be non-0 (in other words,
they could be POWER pins with VSSX signal_names. Similarly
for [Pullup Reference] and [POWER Clamp Reference] could be 0 V
(as with ECL) with corresponding GND model_name terminal VSS.
So [Pin Mapping] labels should not have the stated restrictions.
Bob
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Monday, January 04, 2016 1:03 PM
To: 'IBIS-Interconnect'
Subject: [ibis-interconn] [Die Supply Pads]
All,
I am enclosing a presentation that cleans up the definition of [Die Supply
Pads], defines clear rules on the usage of signal_name and bus_labels, and
outlines a simple implementation of these rules.
I expect that one can create absurd cases which will fail these rules and
pass the existing IBIS parser, but I consider these examples to truly be
absurd, and something that I think all of the EDA companies will not want to
support.
I have requested that Bob represent the following simple example using [Pin
Pad Map]:
A component has 100 VDD pins (P1, P2, .P100) and all of these VDD pins have
the same bus_label (VDD).
The component has 5 VDD die pads (D1, D2, D3, D4, D5), and all of these VDD
die pads have the same bus_label.
Walter
Walter Katz
<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx
Phone 303.449-2308
Mobile 303.335-6156
