[atari7800] Re: DMA TIMING
- From: "Eric Ball" <ek-ball@xxxxxxxxxx>
- To: <atari7800@xxxxxxxxxxxxx>
- Date: Wed, 3 Nov 2004 22:17:26 -0500
> For "3 cycles /tile/graphics byte" does that mean 3 cycles for each
character table entry byte and an additional 3 cycles per bitmap byte for a
total of 6 cycles per character? Then why does the software guide say 6
cycles per indirect and 3 cycles per Character Map access, implying 9 cycles
per character?
It appears that the Indirect cycle counts include the character map access
Hmm, let's see if we can figure this out together. 7.16MHz clock gives 456
cycles per line.
From the Software Guide:
7 CPU cycles (28 MARIA cycles) before DMA
5-9 cycles DMA startup
4-7 cycles DMA shutdown
6 cycles for last line of zone (hmm, this looks to me like a DLL entry read)
Worst case, that leaves 427 cycles per line. Don't know if the EOL header
is included, so take off another 4 cycles for that. 423 cycles left.
Let's drop back to 160A mode, which gives us the fewest bytes per line: 160
pixels/line / 4 pixels/byte = 40 bytes/line. With two bytes per character,
we only need two 5 byte headers, each with a 21 character wide string, each
12 cycles (or is that a typo and it should be 10 cycles?). 399 cycles left.
42 indirect/2 byte @ 9 cycles = 378 cycles, 21 cycles left. Enough for one
4 byte header and a 4 byte sprite.
You can do similar calculations for other graphics modes, but you will run
out of cycles.
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