[SI-LIST] Re: Shoots

David,
see my comments below...



Typically, data sheets spec. max. overshoot at VDD+0.3V and min. =
undershoot as GND-0.3V. Meeting these specs. usually requires adding =
series R's to the offending traces.

>These specs are only applicable at DC (sometimes the manufacturer may have
"forgotten" to mention that in the datasheet), and since in a correctly
designed board there is no chance they would ever by violated; they are
selected with the goal of minimizing the test burden.  The 0.3v value is
chosen as one where the protection diodes are not at all turned on so there
is no need to test, safe operation is guaranteed by design.  In many cases
the reality is that the protection diodes could be turned on continously
without causing any failure(and I have seen some prototype products where
this has been the case due to unintentional supply voltage mismatches).
There is a safe limit to the continous current that could be tolerated based
on electromigration, but no one will spec that for you unless there are
specific circumstances that require it.


I have seen several SDRAM data sheets and at least one CPLD data sheet =
that provide a much more detailed spec. A typical SDRAM spec., for =
instance, allows VDD+2V and GND-2V as long as the duration is not =
greater than 3ns.

>The real limits that I am aware of are elecromigration and gate oxide
breakdown.  The gate oxide breakdown sets the absolute pad voltage limits
based on the maximum safe voltage difference across the gate of any of the
transistors connecting to the pad.  Electromigration is based on the long
term average current through the overshoot clamp structures.  A reasonable
way to spec overshoot to avoid electromigration problems is to specify the
max overshoot current that can be tolerated at a given dutycycle.  The 3ns
overshoot duration you mention is (hopefully) calculated based on the
highest allowable dutycycle at the max frequency of operation of that part.
The overshoot current resulting from a given overshoot voltage depends on
the resistance of the clamp structures and also on the temperature;
increasing temperature shifts the knee of the diode IV curve out which
delays the turn on of the diodes until a higher overshoot voltage is
reached.


1) Are the SDRAM designers doing something unique with the IC pad design =
that allows these larger shoots or are they simply doing a better job =
specifying the extents?

>Some vendors may have to take special measures in their IO design to meet
these requirements, but primarily this is just a case where people thought
more carefully about how to spec this (after many years went by with specs
that just ignored overshoot).


2) What are some of the things that can go wrong if the shoots are too =
large?
2a) Is turning on the protection diodes the only concern?

>gate oxide breakdown and electromigration, see above.

3) What is the root cause of large shoots?
3a) The inductance of the lead frame seems to be a large contributor.

> Overshoot is fundamentally caused by the transmission line nature of the
interconnect.  When the driving impedance of a transmission line (output
driver plus any series termination) is less than the characteristic
impedance of the line and the receiving endpoint of the line is
un-terminated, overshoot will occur.  Some quick simulations of lossless
transmission lines with various drive and load impedances in Pspice or any
SI simulation tool will help to get an understanding of this.  To avoid
confusion, I recommend starting with a waveform period much larger then the
delays of your interconnect so you can see all the reflections completely
die out before the next transition occurs.

best regards,
Jeremy


Thanks,
David
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