[SI-LIST] Re: Shoots
- From: Matthew Russell <boomer@xxxxxxxx>
- Date: Mon, 10 May 2004 21:52:16 -0500
Hi,
The problem is that a true analysis of the real limit is quite complicated.
Besides EM and Gate oxide overstress you also have to worry about
the noise injected into the part power supplies and how it might interfere
with the timing of the interface.
You need to look at the current for each pad and also consider the
EM current as it sums at the VDD and VSS power pads that feed
the IO clamp rail. Depending on the part power and ground ratio
this can easily be the limited factor.
The other interesting thing to consider with this type have high
frequency overshoot (<3ns pulse) is that the package impedance
limits the clamp current.
I have tried to create a set of equations and guidelines for this
in the past and even with some pretty generous simplifications
(averaging the overshoot current across the pulse, etc) things
get a bit ugly pretty fast. Unfortunately I have never had the
chance to get empiracle data to back up the calculations.
I suspect that the 3ns pulse guideline is just based on some simple
diode current curves and EM limit averaging. Though it is definitely
better than a just having the DC 0.3v limit ;)
Matt
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