[SI-LIST] Re: Shoots

  • From: Raymond.Leung@xxxxxxxxxxx
  • To: si-list@xxxxxxxxxxxxx
  • Date: Mon, 10 May 2004 08:43:06 +1000



---------------------- Forwarded by Raymond Leung/sdc on 10/05/2004 08:41
---------------------------


Raymond Leung
10/05/2004 08:41

To:   david.novak@xxxxxxxxxxx
cc:

Subject:  Re: [SI-LIST] Shoots  (Document link: Raymond Leung)

The VDD+0.3/GND-0.3 spec is typically for dc condtions and usually
a chip can tolerate larger transient shoots than these values.  A design
for +2/-2V in 3ns transient is certainly a good design but nothing
particularly unique.  If the shoot is too larger and lasting too long, a large
current will inject into the pin that it is a challenge to the capability of the
design to handle the possible latchup issue, as well as to the handling of
the possible problems of burning out either the internal metal lines, the
contacts to the substrate, the diffusion junctions, or the vias between metal
layers.  In a very large overshot/surge, the cmos gate oxide may also be
burnt, similar to the case of ESD stress.

Regards,
Raymond




"Novak David" <david.novak@xxxxxxxxxxx> on 08/05/2004 06:26:21

Please respond to david.novak@xxxxxxxxxxx

To:   si-list@xxxxxxxxxxxxx
cc:    (bcc: Raymond Leung/sdc)

Subject:  [SI-LIST] Shoots



Typically, data sheets spec. max. overshoot at VDD+0.3V and min. =
undershoot as GND-0.3V. Meeting these specs. usually requires adding =
series R's to the offending traces.

I have seen several SDRAM data sheets and at least one CPLD data sheet =
that provide a much more detailed spec. A typical SDRAM spec., for =
instance, allows VDD+2V and GND-2V as long as the duration is not =
greater than 3ns.

1) Are the SDRAM designers doing something unique with the IC pad design =
that allows these larger shoots or are they simply doing a better job =
specifying the extents?

2) What are some of the things that can go wrong if the shoots are too =
large?
2a) Is turning on the protection diodes the only concern?

3) What is the root cause of large shoots?
3a) The inductance of the lead frame seems to be a large contributor.

Thanks,
David
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