[SI-LIST] Re: On-chip Terminations
- From: Jerry Chow - 7192 <jchow@xxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 13 Jul 2001 11:00:26 -0700
Hi Mark:
I am interested in this pager from PCB West. Can you send
pdf file. Thanks
Mark Alexander wrote:
>
> Matt,
>
> You're right -- the Xcite resistors have a feedback mechanism which matches
> them
> to external reference resistors. Therefore they're adaptive over temperature
> and voltage, and maintain a good impedance match over all corners (process,
> temperature, voltage).
>
> We do not give a tolerance value for these terminations because it doesn't
> make
> sense to. Since there are a number of IO standards that have on-chip
> termination in each IO block, the circuitry is used in a number of different
> configurations. This combined with the active nature of the implementation
> (FETs instead of fixed resistors), makes characterization from a percent
> tolerance standpoint a metric that's not very useful.
>
> Instead, an accurate picture of the behavior of these on-chip resistors can
> best
> be obtained from simulation. The IBIS models contain the information for
> simulation of the Xcite IO. If anyone would like example simulations of this,
> drop me an email.
>
> There's one other point I'd like to make in reference to the tolerance issue.
> When using even a precision external termination resistor, say 1%, changes in
> the impedance of the driver with temperature and voltage can cause much more
> than 1% of impedance mismatch in the channel, leading to a wide range of
> rise/fall times and possible SI problems. Since Xcite compensates the driver
> as
> well as the termination, edges are very consistent and well-matched.
>
> If anyone is interested in additional information on Xcite, there is a paper
> available that I delivered at PCB West. It's on the Proceedings CD, or drop
> me
> an email and I can send it to you.
>
> -mark
>
> "ruston, matt" wrote:
>
> > Patrick:
> >
> > Hi. I've been looking into the Xcite terminations too and cannot find a
> > tolerance. The "resistors" are really multiple parallel FET transistors with
> > different impedances that can get turned on or off to change the overall
> > resistance. It should be much better than an on-chip implanted,
> > poly-silicon, or pinch resistor (15%+). Xcite uses external reference
> > resistors to tweak the on-chip FETs. It is done at startup to dial into the
> > proper range, then it is done in use to make minor adjustments due to
> > voltage and temperature changes. You already know this, just filling in
> > details for the others.
> >
> > Pat Z. was correct to say that a major win with these on-chip terms is stub
> > elimination. It also frees up a lot of PCB real estate and eliminates tons
> > of vias. They are not just for OC48 (don't know why that was thrown in).
> > They can be used on any I/O (in Virtex-II line) and come in several
> > topologies/configs.
> >
> > Still, I'd like to know tolerance, power handling, etc. And no, I'm not a
> > Xilinx salesman.
> >
> > Regards,
> >
> > Matt
> >
> > -----Original Message-----
> > From: Chuck Hill [mailto:chuckh@xxxxxxxxxxx]
> > Sent: Friday, July 13, 2001 11:34 AM
> > To: si-list@xxxxxxxxxxxxx; 'si-list@xxxxxxxxxxxxx'
> > Subject: [SI-LIST] Re: On-chip Terminations
> >
> > Good question.
> >
> > Also, what is the temperature coefficient of these resistors? I'll bet its
> > not the 50ppm/C that the discrete resistors have.
> >
> > Chuck
> >
> > At 09:13 AM 7/13/01, Patrick Francq wrote:
> > >Greetings,
> > > I recently read a brief paper on Xilinx's XCITE technology.
> > >
> > >The only problem is I couldn't find any tolerance values for these on-chip
> > >resistors.
> > >
> > >Discrete resistors have a 1% tolerance.
> > >Buried resistors have a 10-15% tolerance.
> > >On-chip resistors have a ??? tolerance.
> > >
> > >Does anybody have a "ball-park" number on this?
> > >
> > >Thanks all,
> > >Patrick
> > >
> > >
> > >
> > >
> > >Patrick Francq
> > >Hardware Designer / SI Specialist <http://intranet/home.asp>
> > >
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> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
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--
________________________________________________________________________
Jerry Chow, Consumer Application. LSI Logic Ph:408-433-7192
Fax:408-954-4855
Office: 1525 McCarthy Blvd. M/S G-790 Milpitas, CA 95035
Mail : 1551 McCarthy Blvd. M/S G-790 Milpitas, CA 95035
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