[SI-LIST] Re: On-chip Terminations
- From: "Zabinski, Patrick J." <zabinski.patrick@xxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 13 Jul 2001 10:26:58 -0500
Patrick,
The tighter silicon/CMOS processes I've worked with
(limited in number) have on-chip resistor tolerances
around +/-15%. The looser processes are upwards near
20-25%.
For III-IV (GaAs & InP) processes, we've seen
tolerances around 10%.
If you get an "RF" process (some folks tweak their
parameters a bit and extend their design kits to
provide RF-ish elements), the tolerances are generally
tighter than a digital process, and you can generally
get 10% (even in CMOS). Some will even trim the resistors,
and you can get better than 10%.
I am unaware of any commercial process offering tolerances
in the 1% range. Has anyone seen tolerances this tight?
Under the assumption that on-chip resistors have looser
tolerance than off-chip resistors (I believe this is the
case for most/all digital CMOS technologies), signal
integrity is still most often improved by on-chip resistors
due to the removal of the "package stub" effect when
the resistor is located off-chip.
Pat
> I recently read a brief paper on Xilinx's
> XCITE technology.
>
> The only problem is I couldn't find any tolerance values for
> these on-chip
> resistors.
>
> Discrete resistors have a 1% tolerance.
> Buried resistors have a 10-15% tolerance.
> On-chip resistors have a ??? tolerance.
>
> Does anybody have a "ball-park" number on this?
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