[SI-LIST] Re: Is Impedance Enough for Describing the PDS?
- From: steve weir <weirsp@xxxxxxxxxx>
- To: Chris.Cheng@xxxxxxxxxxxx, "'Larry.Smith@xxxxxxx'" <Larry.Smith@xxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Fri, 16 Jul 2004 13:47:48 -0700
Chris, it is interesting that you suggest such a fast converter. The
issues with such a fast converter have traditionally been losses due to
switching and in the Fe. I have had some ideas from time to time but have
never been able to find a suitable solution.
Steve.
At 12:50 PM 7/16/2004 -0700, Chris Cheng wrote:
>I think the power supply response is just as important as the impedance. If
>you can get your DC/DC to beat faster, the amount of bulk caps needed to
>hold the low end of the impedance can be minimized. One of these days, some
>very smart people will come out with a 10-100MHz DC/DC. Things will get very
>interesting.
>
>-----Original Message-----
>From: Larry Smith [mailto:Larry.Smith@xxxxxxx]
>Sent: Friday, July 16, 2004 10:41 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Is Impedance Enough for Describing the PDS?
>
>
>Scott and Steve have both had some good comments on the importance of
>mounting inductance for decoupling capacitors. The mounting
>inductance is almost inversely proportional to the number of vias used
>to attach the capacitor to the power planes and proportional to the
>length of the vias (depth to the first plane). The number of high
>frequency capacitors required to meet a PDS target impedance is nearly
>proportional to the mounting inductance over the frequency range that
>we care the most about. So in a sense, the number of vias is
>important, the number of capacitors is not.
>
>Ten years ago, the typical mounting inductance for decaps was 3 to 5
>nH as we used traces to vias; to power planes; that were buried in the
>middle of our boards; usually with 14 mils or more separation between
>planes. We sometimes shared vias between 2 or more caps! As
>mentioned by Scott, it is now possible to attach capacitors with a
>total mounting inductance of 200pH or less. So the number of
>capacitors necessary to meet a target impedance a decade ago was 20
>times more than what it is today. Actually, the number of capacitors
>has stayed about the same and the target impedance has dropped by
>about a factor of 20.
>
>When you think about it, all we really need is a single ideal 1 uF
>capacitor connected to our PDS. The impedance of a 1 uF capacitor at
>1 MHz is 159 mOhms. It is 15.9 mOhms at 10 MHz, 1.59 mOhms at 100 MHz
>and 0.159 mOhms at 1 GHz. Imagine that, a PDS with much less than 1
>mOhm at a GHz! And all you need is one ideal capacitor! The moral of
>this story is that a low impedance PDS at high frequency has very
>little to do with capacitance and is all about managing the parasitic
>inductance.
>
>Small power islands work great for core power. Just put enough
>capacitors (and vias) in parallel that you achieve the target
>impedance up to the desired corner frequency. It does not take too
>many well-mounted capacitors in parallel to do this. The biggest
>problem is that the impedance of the parallel combination of all caps
>mounted on the plane becomes less than the impedance of the power
>planes used to bring the current into the chip. This is where the
>thin power plane dielectric (BC) comes in. Once again, it is not
>about capacitance but is all about spreading inductance. If the
>impedance of the conduit is higher than that of the parallel caps,
>don't bother putting any more caps on the board..
>
>The subject of this thread is, "Is Impedance Enough for Describing the
>PDS?" For the purpose of power integrity (getting the power to the
>consumer when it is required and stop delivering power to the consumer
>when it is not required), the answer is a resounding YES! If the chip
>circuits look out and see their target impedance up to a frequency
>that is related to the transient rise time, they are happy. If the
>chips are happy, they don't make EMI noise. EMI noise is just a
>result of chips demanding current from a PDS that is too high in
>impedance. Current drawn from a high impedance implies power injected
>into the PDS and that is trouble. Manage the PDS impedance at the
>power consumer and (PDS related) EMI problems will be greatly reduced
>or go away completely.
>
>regards,
>Larry Smith
>(still at) Sun Microsystems
>
>PS - Boy, I sure miss Ray!
>
>steve weir wrote:
> >
> > Zhangkun,
> >
> > As I stated, the mounted inductance of IDC's and X2Y's is less than 1/3
>the
> > mounted inductance of ordinary 0603's using optimized two via mounts. The
> > inductance of the IDC / X2Y capacitors by themselves is even less, but as
> > you note the attachment inductance interferes. The reason that IDCs do
> > very well is that it takes four times as many via holes as a regular
> > capacitor. Done correctly, there is an almost proportionate decrease in
> > the attachment inductance. So, an IDC can be viewed as four 0603s, in
> > parallel but with only one part to mount.
> >
> > The physics of the X2Y are a bit different. In cooperation with X2Y, I
> > have developed optimized mounts for X2Ys that use six vias and get results
> > essentially identical to the IDC with optimal mounts. This has been
> > verified by both simulation and measured results. The IDC's require 33%
> > more vias, and a much higher component cost to do the same decoupling job
> > as X2Ys.
> >
> > Using either X2Y or IDCs we can cut component count by 3:1 or
> > better. Using X2Ys we reduce the BOM cost as well. Both Teraspeed and I
> > offer services to optimize PDS design to suite needs whether it is
>density,
> > cost or some combination. There are probably other consultants available
> > who do as well.
> >
> > Regards,
> >
>
>Scott McMorrow wrote:
> >
> > Zhangkun,
> >
> > Zhangkun wrote:
> >
> > >How about the value of the inductance of these kind of capacitors? When
>the cap is soldered on the PCB, there is leading inductance of about 1nH.
>This could not be eliminated by better caps.
> > >
> > Actually, better designed capacitors and better mounting structures do
> > help. Steve and I both have developed mounting structures for some of
> > these capacitors that are down in the 200 pH range, with a total mounted
> > device inductance below 400 pH. It's all a matter of physics and good
> > design practices. With X2Y and IDC capacitors, we can obtain between a
> > 3 and 4-to-1 part count reduction over 0603 capacitors with the best
> > designed mounting solution.
> >
> > regards,
> >
> > scott
> >
> > --
> > Scott McMorrow
> > Teraspeed Consulting Group LLC
> > 121 North River Drive
> > Narragansett, RI 02882
> > (401) 284-1827 Business
> > (401) 284-1840 Fax
> > (503) 750-6481 Cellular
> > http://www.teraspeed.com
> >
> > Teraspeed is the registered service mark of
> > Teraspeed Consulting Group LLC
> >
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