[SI-LIST] Re: Is Impedance Enough for Describing the PDS?
- From: "Vijay B" <vijayis@xxxxxxxx>
- To: weirsp@xxxxxxxxxx, "Zhangkun" <zhang_kun@xxxxxxxxxx>, "Abhijit Mahajan" <amahajan@xxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Fri, 09 Jul 2004 19:07:29 -0500
Hello,
I am a student at SUNY and I am studying power integrity on a
PCB/package. I am studying it by analyzing the structural resonances due to
standing waves formed between the power and ground planes on a 2 plane
board.Different modes being excited being the cause of the different
resonances.
We feel that is possible to a reasonable extent to control the
position of the first resonant frequency on a given board - without the use
of decoupling capacitors. Possible upto the multi-GHz range. We have a
preliminary design on a 2 plane board without any components on it, and we
have verified our results with simulation tools and a network analyzer.
I am very interested to know what the standards in the industry
are. For any given processor - upto what frequency is the power distribution
system designed to be stable. (what percent of the processor speed).
We considered only TEM waves. I am curious to know if TE and TM
waves are also being considered or if/when their effects will start being
felt..
Any comments would be greatly appreciated.
thanks,
regards,
vijay
----- Original Message -----
From: steve weir
Date: Fri, 09 Jul 2004 14:06:41 -0700
To: Zhangkun ,Abhijit Mahajan , si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Is Impedance Enough for Describing the PDS?
>Zhangkun,
>
>As I stated, the mounted inductance of IDC's and X2Y's is less than 1/3 the
>mounted inductance of ordinary 0603's using optimized two via mounts. The
>inductance of the IDC / X2Y capacitors by themselves is even less, but as
>you note the attachment inductance interferes. The reason that IDCs do
>very well is that it takes four times as many via holes as a regular
>capacitor. Done correctly, there is an almost proportionate decrease in
>the attachment inductance. So, an IDC can be viewed as four 0603s, in
>parallel but with only one part to mount.
>
>The physics of the X2Y are a bit different. In cooperation with X2Y, I
>have developed optimized mounts for X2Ys that use six vias and get results
>essentially identical to the IDC with optimal mounts. This has been
>verified by both simulation and measured results. The IDC's require 33%
>more vias, and a much higher component cost to do the same decoupling job
>as X2Ys.
>
>Using either X2Y or IDCs we can cut component count by 3:1 or
>better. Using X2Ys we reduce the BOM cost as well. Both Teraspeed and I
>offer services to optimize PDS design to suite needs whether it is density,
>cost or some combination. There are probably other consultants available
>who do as well.
>
>Regards,
>
>
>Steve.
>At 07:46 PM 7/9/2004 +0800, Zhangkun wrote:
>>Dear steve
>>
>>IDC's, very expensive
>>X2Ys, more than cheapy 0603 MLCCs but a lot less than IDCs
>>NEC Proadlizer ( consult NEC on price )
>>
>>How about the value of the inductance of these kind of capacitors? When
>>the cap is soldered on the PCB, there is leading inductance of about 1nH.
>>This could not be eliminated by better caps. When the PCB is dency, the
>>decoupling caps have to be put on the bottom. The leading inductance is
>>larger. When the trace is used for PDS, the decoupling caps have to be put
>>near the IC. How many caps is enough?
>>
>>What is the paper title which you mentioned, the Chris Cheng's?
>>
>>Best Regards
>>
>>Zhangkun
>>2004.7.9
>>
>>----- Original Message -----
>>From: "steve weir"
>>To: "Abhijit Mahajan" ;
>>Sent: Friday, July 09, 2004 4:40 PM
>>Subject: [SI-LIST] Re: Is Impedance Enough for Describing the PDS?
>>
>>
>>>Abhijit, yes localization is an approach that can be very helpful in
>>>reducing or completely eliminating cavity resonance issues. For a long
>>>time we have been able to get away with letting planes perform dual
>>>duty: wide low impedance lumped conductors for power, and the return side
>>>of signal transmission lines. But we are long past the point where signal
>>>spectra is way beyond board lambda / 4. for common plane size / Er
>>>combinations. Continued dual-use under these circumstances is an
>>>invitation to EMC nightmares, and greatly complicates PDS
>>realization. But
>>>it does keep consultants like me busy. Sigrity, and Ansoft sell tools to
>>>try and manage these problems. T he tools are very nice, but I think the
>>>tools address the wrong problem.
>>>
>>>If we "simply" eliminate the cavities ( OK shrink them so that they are
>>not
>>>problematic ), as you suggest then I think we are on the right
>>>track. There is documentation out that clearly shows the economic
>>benefits
>>>of islanding power. In one recent paper, the author demonstrated that a
>>>board with islanded power and 20mil power / ground separation performed
>>>almost identically EMC-wise to the same size assembly using 2mil BC. The
>>>tool and material vendors probably don't like hearing this.
>>>
>>>Islanding power presents challenges with stack-up planning and
>>routing. We
>>>still have to:
>>>
>>>1) Create a local low imped ance on the island, and
>>>2) Get the DC current to the island
>>>
>>>I see the tool opportunities in supporting these efforts, as the physics
>>>and economics will really demand it. On the low-impedance island
>>technique
>>>end, I am a big fan of low inductance capacitors and optimized attachment
>>>techniques. The really low inductance capacitors that can be fitted to a
>>>PWB today are:
>>>
>>>IDC's, very expensive
>>>X2Ys, more than cheapy 0603 MLCCs but a lot less than IDCs
>>>NEC Proadlizer ( consult NEC on price )
>>>
>>>If done correctly, islanding can save a bundle, and goes directly to
>>one of
>>>Chris Cheng's pet mantra's that B/C is a solution looking for a
>>>problem. We can avoid such problems and there fore the cost of B/C.
>>>
>>>Steve.
>>>At 01:06 PM 7/9/2004 +0530, Abhijit Mahajan wrote:
>>>>Steve/Others.
>>>>
>>>>Would it be better then to reduce the area of power planes as much as
>>>>possible(by
>>>>localizing the power planes to only cover the pins that need it) and
pack
>>>>the decoupling there?
>>>>islands of same voltage can be then connected with wide traces to the
>>>>nearest bulk cap
>>>>And finally brought together at the regulator.
>>>>
>>>>This can be vaguely be described as a "star topology" for power
>>>>distribution.
>>>>
>>>>Does anyone think there is any value in this appproach? Has it been
>>>>discussed before?
>>>>
>>>>
>>>>##I am assuming all signal routing is over a common ground plane.
>>>>
>>>>
>>>>Thanks!
>>>>
>>>>Abhijit.
>>>>
>>>>
>>>>-----Original Message-----
>>>>From: si-list-bounce@xxxxxxxxxxxxx
>>[mailto:si-list-bounce@xxxxxxxxxxxxx] On
>>>>Behalf Of steve weir
>>>>Sent: Friday, July 09, 2004 6:04 AM
>>>>To: zhang_kun@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
>>>>Subject: [SI-LIST] Re: Is Impedance Enough for Describing the PDS?
>>>>
>>>>
>>>>Zhangkun, the problem is that the PDS overlaps both signal integrity and
>>>>EMC compliance. If the system rules are done right, then the PDS
>>>>d ecoupling problem will eventually reduce to an impedance profile. But
>>>>that profile is both spatial and frequency dependent. If I shove all the
>>>>decoupling capacitors into one corner of the board I get a very
different
>>>>result than if I distribute them.
>>>>
>>>>Steve.
>>>>At 08:04 AM 7/9/2004 +0800, zhangkun 29902 wrote:
>>>>>Dear all
>>>>>
>>>>>When talking about power delivery system with other engineer, there are
>>>>>a
>>>>>lot of element to describe the PDS, such as energy storage, decoupling,
>>>>>bypassing, and so on. I think all these parameter could be described by
>>>>>one element, impedance of PDS.
>>>>>
>>>>>Is my point right? Is impedanc e enough for describing the PDS?
>>>>>
>>>>>Best Regards
>>>>>
>>>>>Zhangkun
>>>>>2004.7.9
>>>>>
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>
>
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