[SI-LIST] Re: How to test the power ripple ?
- From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
- To: icer world <icermail@xxxxxxxxx>
- Date: Mon, 19 May 2008 09:05:54 -0400
There are three possible design considerations around power
distribution networks (PDN) on boards:
1) supplying clean power to electronics (PI)
2) serve as return path to signals (SI)
3) make sure that radiation from the PDN is within acceptable limits (EMC)
(1) is obviously the most important and not optional. (2) depends on
the design: if the particular piece of PDN does not serve as signal
reference and noise coupled from other PDN pieces is negligible, this
item is irrelevant. (3) is highly dependent on mechanical construction
of the board, size of system, box/chassis construction, I/O connections;
we may or may not be able to ignore it safely.
When all three must be considered, the design and validation has to be
done to meet the most stringent requirement of the three. Core and IO
power distributions are good examples to show some permutations.
Consider for instance a high-power core PDN. If the core planes do not
serve as signal reference, (2) is out and we are left with (1) and (3).
The crossover frequency between PCB and package for core PDN may be in
the MHz range, so strictly just to validate (1), a 20MHz BW may be
sufficient. Core clock, however, leaking out to the PCB, which may not
upset function (1), may severely degrade EMC performance (3), so it is
always a good idea to test for at least the first few harmonics of the
core clock frequency (second harmonic being the most notorious).
IO PDN, if used also as signal reference, may be sensitive to noise in
the entire BW of the receivers. If noise couples differently to signal
lines versus clock lines, low frequencies also matter, otherwise it will
be sensitive mostly to high frequency noise, falling into the signaling
bandwidth.
My understanding is that the 20MHz BW limitation comes from practical
considerations: on noisy production floors a wider BW will let spurious
noise from outside contaminate the data. Still today, data sheets of
many DC-DC converters specify the periodic and random noise with a 20MHz
BW, because this is what can be easily measured. However, today's fast
DC-DC converters usually produce high-frequency burst ringing along the
switching edges in the hundreds of MHz frequencies; it can mess up
reference clocks and signaling, but we completely miss it with a 20MHz
measurement BW.
Measuring wide-band time-domain PDN noise is not easy; improperly
connected probes, big cable loops, common-mode noise, finite
cable-shield immunity against strong external intefereing fields all
make these measurement very challenging. This, however, does not mean
that the wide-band noise on the PDN is not important to know.
Regards,
Istvan Novak
SUN Microsystems
icer world wrote:
> hello all:
> When test the ripple of the power of a board ,It's said that I should test
> it below 20MHz.But I found that it's much defferent when I test the ripple
> in the full band width frequency.As I think we should test the ripple without
> any frequency limit ,or we can't observe the noise produced by other devices
> which can couple into the power system .I hope someone will give me some
> !advice,thanks
>
>
>
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