[SI-LIST] Re: Chip capacitance effect for SSN simulation
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 17 Oct 2011 08:13:12 +0200
Hello, me again ...
some short comments on my previous post:
Of course if you do not use a full 3D Field solver you need a special
needle modeling. I could imagine, that the Bondwire models in Momentum
could allow a nice modeling ..
Of course VDD/VSS is also to be considered, as this could cause also
some noise with some specific activation cycles (also I doubt that DDR2
with e. g. 533MHz for DDR2-1066 can stimulate a 1GHz resonance on VDDQ
or VDD)
Hermann
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schrieb Hermann Ruckerbauer:
> Hello,
>
> just as short feedback to Ravva's answer:
>
> 1) The die capacitance(C_Comp) in the IBIS is the parasitic input
> capacitance due to ESD, routing, Driver, Receiver ..
> It is NOT the decoupling capacitor between VDDQ and VSSQ!
>
> 4) I agree that a full 3D solve is too big for the system I'm expecting.
> There are other tools out that will do this job better. As ADS user I
> would give Momentum a try ..
>
>
> Hermann
>
> Our next Events:
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> Signal Ingegrity Seminar "Open the Black Box of Signal Integrity"
> at TH Aalen on 29th October 2011
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>
> Check our website or contact us for details
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
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> Tel.: +49 (0)9938 / 902 083
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>
> schrieb Poorna Chander Ravva:
>> Hi Cris,
>> 1. As far as I know the IBIS model should include the one die capacitance
>>
>> 2. May be you can just confirm with the silicon vendor
>>
>> 3. Also the frequency range of the anti resonance for your PDN is
>> important. If the resonance is generally around 1GHz range, then it might
>> be contributed because of the lack of the on die capacitance.. if the
>> resonance is much much lower in frequency it is contributed by either the
>> lack of your package capacitance (since you did not include that anyway)
>> and or board capacitance
>>
>> 4. Regarding the HFSS simulation: if you are generating your whole power
>> delivery network model in HFSS it would be very difficult to solve. I
>> would use tools like PowerSI or Ansoft SIwave to generate the PDN models
>> and then incorporate the connector models from the HFSS into your final
>> SSN SPICE simulation...
>>
>> Thanks,
>> PoornaChander Ravva
>>
>>
>>> Hi folks
>>>
>>> thanks for your feedback.
>>> I had to reduce the number of power pins in HFSS simulation otherwise the
>>> full 3D model with all power pins was to huge to simulate.
>>>
>>> So I reduced 46 pwr needles of I/O pwr to only 6 around of my total 10 I/O
>>> I'm simulating for SSN.
>>>
>>> Cheers
>>> Cris
>>> Inviati dal mio telefono Nokia
>>> ----Messaggio Originale----
>>> Da: Michael Greim
>>> Inviati: 16/10/2011, 15:13
>>> A: steve weir
>>> Cc: si-list@xxxxxxxxxxxxx
>>> Oggetto: [SI-LIST] Re: Chip capacitance effect for SSN simulation
>>>
>>>
>>> Great points Steve (as always). Cristian, a simulation
>>> is only as good as its ability to properly mirror the actual
>>> correlated test setup. As you strip this that and the other
>>> thing out, the sim and the hardware behavior will become very
>>> different from one another. Set up some test cases with
>>> your queries and see if the behaviors are convergent or
>>> divergent.
>>> Why did you "have to" reduce the number of power pins?
>>>
>>> Build up a better relationship with your vendor and tell them
>>> what you are looking for and why and you might be quite
>>> surprised what they give you. Perhaps even an RLC matrix
>>> or two and with a story relating of other customers who have
>>> run into similar issues.
>>>
>>> Check out my quote from Mr fleischmann below. Works
>>> great for a number of things in real life and the simulated
>>> behavior thereof including SI/PI sims.........
>>>
>>> -Michael.
>>>
>>> We will either find a way or make one -Hannibal
>>>
>>> In the middle of every difficulty lies opportunity -Al Einstein
>>>
>>> If you're not getting the results you want with the
>>> current approach, move on and try something else. -A. Fleischmann
>>>
>>>
>>> On Sun, Oct 16, 2011 at 5:39 AM, steve weir <weirsi@xxxxxxxxxx> wrote:
>>>
>>>> You need a model of the silicon that includes the on-die capacitance.
>>>> You can try to obtain this, or if it is not available, then derive it
>>>> from measurements. The complexity of the model that you construct
>>>> depends on how much accuracy you need. You will still face the same
>>>> challengess as others in the ATE business when dealing with the parallel
>>>> bus structure of DRAM switching with very small rise and fall times, and
>>>> the inductance of your probing interconnects.
>>>>
>>>> Steve.
>>>>
>>>> On 10/16/2011 2:25 AM, Cristian Gozzi wrote:
>>>>> Hi SI members
>>>>> I'm simulating DDR2 SSN for a Probe Card system
>>>>>
>>>>> for those that are not familiar with this application, Probe Card is
>>>> an
>>>>> hardware application to physical connect DIE pads/bumps at wafer level
>>>> to
>>>>> ATE system during Electric Wafer Sort
>>>>> In my case Probe-Card is build by a vertical needles that touch DIE
>>>> pads
>>>> +
>>>>> PCB
>>>>>
>>>>> During frequency domain analysis of my system, I got a strong PDN peak
>>>>> impedance around 1GHz
>>>>> This peak impedance was due to anti-resonance effect between PCB PDN
>>>> system
>>>>> and needle PWR parasitic effect
>>>>>
>>>>> so during time domain analysis I got a strong and unreasonable AC
>>>> noises
>>>>> also with only 2 switching DQ
>>>>>
>>>>> In my spice deck I only used IBIS model provided by silicon vendor and
>>>> I
>>>>> excluded RLC package effects, since my application is contacting
>>>> directly
>>>>> wafer.
>>>>>
>>>>> I think I should include chip power rail capacitance effect in order
>>>> to
>>>>> filter high freq noises.
>>>>>
>>>>> But my question is: which C and R value should I use?
>>>>>
>>>>> Is these value included in IBIS model?
>>>>>
>>>>> NOTE: consider that I had to reduce number of PWR needles used for
>>>> HFSS
>>>>> simulation, so I only selected those needles around my 8 DQ + 2 DQS
>>>>>
>>>>> So I think I should put a lower value of chip capacitance than total
>>>> one
>>>>> Any comments from expert are more than welcome
>>>>>
>>>>> Thanks in advance
>>>>>
>>>>> Regards
>>>>> Cris
>>>>>
>>>>>
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>>>>>
>>>> --
>>>> Steve Weir
>>>> IPBLOX, LLC
>>>> 150 N. Center St. #211
>>>> Reno, NV 89501
>>>> www.ipblox.com
>>>>
>>>> (775) 299-4236 Business
>>>> (866) 675-4630 Toll-free
>>>> (707) 780-1951 Fax
>>>>
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