[SI-LIST] Chip capacitance effect for SSN simulation

Hi SI members
I'm simulating DDR2 SSN for a Probe Card system

for those that are not familiar with this application, Probe Card is an
hardware application to physical connect DIE pads/bumps at wafer level to
ATE system during Electric Wafer Sort
In my case Probe-Card is build by a vertical needles that touch DIE pads +

During frequency domain analysis of my system, I got a strong PDN peak
impedance around 1GHz
This peak impedance was due to anti-resonance effect between PCB PDN system
and needle PWR parasitic effect

so during time domain analysis I got a strong and unreasonable AC noises
also with only 2 switching DQ

In my spice deck I only used IBIS model provided by silicon vendor and I
excluded RLC package effects, since my application is contacting directly

I think I should include chip power rail capacitance effect in order to
filter high freq noises.

But my question is: which C and R value should I use?

Is these value included in IBIS model?

NOTE: consider that I had to reduce number of PWR needles used for HFSS
simulation, so I only selected those needles around my 8 DQ + 2 DQS

So I think I should put a lower value of chip capacitance than total one

Any comments from expert are more than welcome

Thanks in advance


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