[SI-LIST] 2D vs 3D EM based signal integrity simulators
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 14 Jan 2010 22:04:19 -0000
Hi experts,
I would like to ask your opinions about the following:
Which one is "better", using 2D or 3D electromagnetics computation based
signal integrity simulators?
The point is to get a voltage-time waveform at/inside the receiver, with
accurate enough electromagnetic modeling of the PCB interconnections. We
should get realistic waveforms even on boards without a perfect groung
plane. The non-perfect ground plane is the main reason why this topic has
been opened, on real product, the ground plane is never perfect for all the
signals on all the buses. For the following interfaces: 133MHz PCI-X,
DDR1-400MHz, DDR2, DDR3-1066MHz, SATA, PCI-express-2.5Gbps, 10Gig ethernet.
If there are splits in the reference planes, it forces the return currents
away from the traces cousing reflections, impedance change, EMI, and
crosstalk. We want to se the effect of these as well. If someone is not an
academic, but a practising design engineer, then he/she knows that to have
perfect reference planes (current return paths) on a computer motherboard
(or similar product) is mostly just a dream. Some people say "dont route the
critical signals over discontinuities", but if we have 500 of these signals
on a 160mm x 80mm x86-SBC board, then we just can not make it. this is when
we have to simulate how bad it is for the signal integrity.
For 2D, I would mention Hyperlynx as an example. As far as I know, it finds
segments of the PCB trace structure where the cross section geometry is
constant (for example 2 traces 0.2mm gap for 22 milimeter length, then they
get closer to 0.15mm for another 10mm, so then the program divides it to 2
segments), then runs a 2D field solver (meshes the cross-section) to get
per-unit-length parameters (maybe tline-Z0 or R, L, G, C), then internally
runs a time domain simulation using these lumped parameters and the IBIS
models of the buffer circuits to get the final time domain waveforms. This
segmentation does not deal very well sith layer transitions, and the 2D
computations (by their nature) presume perfect reference planes.
For 3D, I would mention the Agilent ADS+Momenum macromodeling simulator. It
does not take segment-models, but meshes the whole 3D geometry and runs a
frequency domain field-solver to get a touchstone macromodel, then we build
a simulation circuit with this model and the IBIS models to run the time
domain simulation to get the voltage/time signal waveforms.
Advantages, 2D:
-fast, we get results within a minute.
-it can use a lot higher density on the cross-section mesh, since it only
meshes the cross sections, and the problem-size is still lower than it is
for a 3D simulation. This leads to more accurate impedance and skin-effect
computations.
-we can simulate a full memory bus with 64 signals and get a timing result
spreadsheet.
-it runs on a normal desktop PC.
Disadvantages, 2D:
-does NOT model non-perfect reference planes: plane splits, antipad-fields,
layer transitions, stitching vias, decoupling capacitor return paths...
-when a signal changes layer on a eg 14 layer board, the return currents
have to follow it to the reference planes of the new signal layer. this can
be modeled only in 3D simulation. The 2D simulator models a via with lumped
RLC elements. It presumes that the return current disappears from the plane
at the signal via and reappears on the other reference planes by some magic.
This obviously does not happen on a real board. Most of the cases we just
can not afford to have stitching vias at every signal via, so the lack-of
them should be modeled. The 3D simulators simulate this.
Advantages, 3D:
-it does exactly model non-perfect reference planes: plane splits,
antipad-fields, stitching vias, decoupling capacitor return paths...
-when a signal changes layer on a eg 14 layer board, the return currents
have to follow it to the reference planes of the new signal layer. this can
be modeled only in 3D simulation. The 2D simulator models a via with lumped
RLC elements. It presumes that the return current disappears from the plane
at the signal via and reappears on the other reference planes by some magic.
This obviously does not happen on a real board. Most of the cases we just
can not afford to have stitching vias at every signal via, so the lack-of
them should be modeled. The 3D simulators simulate this.
Disadvantages, 3D:
-slow, it may take days to get a result for a difficoult net. (eg. a signal
on a DDR3 DIMM memory fly-by address bus)
-because of the memory limitations of the available computers, we can not
have very dense mesh in the 3d structure. can it be dense enough at all, for
example with a server-PC with quad-Xeon + 24GB memory? If the cross-section
mesh is not dense enough, then the skin effect and impedance values may not
be modeled accurately.
-we can only model 1-2 traces at a time, even that takes hours/days.
It is another story that we can do 3D computation also on small localised
board areas, then chain these models for simulation. For example only on a
single via transitions to speed up our simulation. But then it can not be
applied to every problem. for example if we dont have a stitching GND
via-ring around every single signal via, then a the return current flows out
of our model... If we design a test vehicle with one 10Gbps signal and SMA
connctors then we can have stitching-via ring around, but route 32 of these
signals out from under a 40mm by 40mm BGA next to a memory bus !
The timing is very tight on a DDR3-1066MHz bus or on a PCIe-kink, so every
little detail problem on the board may cause the system to fail. They
operate with almost zero margin when the board is well-designed. Can we
predict these with any of the methods? (2D or 3D)
regards,
Istvan Nagy
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