[PCB_FORUM] Re: Dual Plane VIA Connection Question
- From: "Gerry Meier" <gerry.meier@xxxxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Sun, 12 Mar 2006 09:29:05 -0800
Pat,
There's a property to remove those adding "vias_allowd" to the route
_keepout will allow vias without DRC's
Gerry
Gerry Meier
Sr. PCB Designer
Freedom CAD Services, Inc.
Voice: (603) 864-1300 x1350
AL Voice: (256) 417-6944
Email: gerry.meier@xxxxxxxxxxxxxx
Visit us at www.freedomcad.com <http://www.freedomcad.com/>
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of westfeldt
Sent: Sunday, March 12, 2006 8:53 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Dual Plane VIA Connection Question
I would create a route keepout on the internal layer, so that automatic
plane void clears the area around the vias. I would then have to
accept, and perhaps note, the drcs that would be caused by the two vias
being in the middle of the route keepout.
Patrick Westfeldt, Jr.
720-406-0887
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Vince Di Lello
Sent: Saturday, March 11, 2006 3:27 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Dual Plane VIA Connection Question
Here's hoping one of you great designers out there (and Allegro expert)
can help me out ... in the picture below you will see a light blue
external (Top Side) 3.3V plane. Inside this board (but not shown) is a
separate 3.3V plane. What I would like to do is have the (3) vias at the
top of the picture (coming off the electrolytic cap) make connection
with the internal 3.3V plane and then connect to the electrolytic cap
with traces as shown in the picture. The 3.3V then travels down this
small external plane coming into contact with some other capacitors and
ultimately ends at the two vias at the bottom which carry the current
from the top side of the board to the bottom side of the board where in
turn there are two traces that connect to two bottom side pads of a
bottom side connector. Now for my problem - the two vias at the bottom
of the light blue area are now also connected to the INTERNAL 3.3V
master plane (for clarity sake I did not turn that plane on). I DO NOT
WANT them to connect to the internal 3.3V plane. I want to force the
3.3V signal to have to travel through the caps and then into the
connector pads on the external layer only. Is there a setting or a
property that I can add to those two vias so that they get connected to
the small external 3.3V copper plane, but NOT to the INTERNAL 3.3V
master plane?
Any help, especially on a weekend, would be greatly appreciated. Thanks
in advance and I hope all who are listening will have a great weekend -
at least what is remaining of it. Thanks again.
Vincent Di Lello, CID+
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