Good morning to all .... and thanks to all for the great suggestions. I greatly appreciate the fast and wonderful help I always get with this forum .... further to (and in closing) this discussion .... one credo that I try to follow with each hurdle I face with the design tool set is to always try and come up with a solution that is as fool proof as possible should another designer pick up the design sometime in the future so that he/she does not accidently cause errors due to the fact that they were not aware of something. This unfortuantely is the byproduct of too many work arounds in the design world with today's tool sets. Therefore, with this problem, taking suggestions from everyone, I was able to come up with (what I think is) a fool proof solution but with a little different twist. Instead of using a conventional VIA, due to it's lack of flexability in not being able to add individual route keepout too, I have decided to use a conventional PART (SYMBOL) using the same size padstack as the via. The negative drawback is that each one that I need will have to be added to the schematic, but the major upside is that I can add a Route Keepout for a specific layer. (An FYI on this - when you first create your symbol, your only choices for adding a Route Keepout are Top, Bottom & All. What I did was chose Top and then when I brought the part (symbol) into my design, because my design was (8) layers, I was able to Change the Route Keepout plane for that part (symbol) from Top to the Inner Layer that I needed). We simply call these parts Vitual Pins or Virtual Vias and simply turn off (or delete) the reference designation as they are not required for visibility on the final assembly. Thanks again to all who provided some great feedback. I hope you all enjoy what is left of the weekend. Vincent Di Lello, CID+ ________________________________ From: icu-pcb-forum-bounce@xxxxxxxxxxxxx on behalf of westfeldt Sent: Sun 3/12/2006 6:52 AM To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] Re: Dual Plane VIA Connection Question I would create a route keepout on the internal layer, so that automatic plane void clears the area around the vias. I would then have to accept, and perhaps note, the drcs that would be caused by the two vias being in the middle of the route keepout. Patrick Westfeldt, Jr. 720-406-0887 ________________________________ From: icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Vince Di Lello Sent: Saturday, March 11, 2006 3:27 PM To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] Dual Plane VIA Connection Question Here's hoping one of you great designers out there (and Allegro expert) can help me out ... in the picture below you will see a light blue external (Top Side) 3.3V plane. Inside this board (but not shown) is a separate 3.3V plane. What I would like to do is have the (3) vias at the top of the picture (coming off the electrolytic cap) make connection with the internal 3.3V plane and then connect to the electrolytic cap with traces as shown in the picture. The 3.3V then travels down this small external plane coming into contact with some other capacitors and ultimately ends at the two vias at the bottom which carry the current from the top side of the board to the bottom side of the board where in turn there are two traces that connect to two bottom side pads of a bottom side connector. Now for my problem - the two vias at the bottom of the light blue area are now also connected to the INTERNAL 3.3V master plane (for clarity sake I did not turn that plane on). I DO NOT WANT them to connect to the internal 3.3V plane. I want to force the 3.3V signal to have to travel through the caps and then into the connector pads on the external layer only. Is there a setting or a property that I can add to those two vias so that they get connected to the small external 3.3V copper plane, but NOT to the INTERNAL 3.3V master plane? Any help, especially on a weekend, would be greatly appreciated. Thanks in advance and I hope all who are listening will have a great weekend - at least what is remaining of it. Thanks again. Vincent Di Lello, CID+