[SI-LIST] Re: via location
- From: "Peter" <yonghui.sky@xxxxxxxxx>
- To: <bowden.ivor@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 6 Jun 2014 10:45:07 +0800
Per my experience, the noise is generated inside the high speed digital
chip, and it will spread to power supply plane. So the decap is filtering
the noise generated by the chip first, not filtering noise from the power
supply in high speed multi-layer design. In this case , via location is not
so important.
Peter
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Ivor Bowden
Sent: Thursday, June 05, 2014 12:50 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] via location
Hi SI community,
Consider a device power pin, a power plane, and a decap (of
course power comes in pairs, let's just consider one leg
now). Assume device has di/dt requirements high enough to
make this discussion relevant.
Say physical constraints allow you to place decap a few (or
several) mm away from power pin, on same side of PCB, and
connect power pin to decap with relatively wide trace.
Say physical constraints allow you a single via to plane,
e.g. microvia in pad. Should that via be at the power pin
pad or at the decap pad?
I've seen app notes state either of these ways. My
consideration is if via is at decap pad, then there is more
inductance to device resulting in more noise in device (e.g.
ground bounce). If via is at device pin, then there is more
inductance to decap, resulting in more noise on plane.
Looking for insight here. Comments?
Thanks,
Ivor
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