[SI-LIST] Re: via location
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 04 Jun 2014 22:37:45 -0700
There are multiple answers because the answer depends on the
circumstances. For most boards where the power planes are close to the
surface via'ing at the IC will make power for the IC the quietest.
Exceptions occur where the planes are far from the device surface. In
those cases with a wide enough surface patch, the IC will see a lower
PDN impedance connected first to the capacitor.
Steve
On 6/4/2014 9:49 PM, Ivor Bowden wrote:
> Hi SI community,
> Consider a device power pin, a power plane, and a decap (of
> course power comes in pairs, let's just consider one leg
> now). Assume device has di/dt requirements high enough to
> make this discussion relevant.
>
> Say physical constraints allow you to place decap a few (or
> several) mm away from power pin, on same side of PCB, and
> connect power pin to decap with relatively wide trace.
>
> Say physical constraints allow you a single via to plane,
> e.g. microvia in pad. Should that via be at the power pin
> pad or at the decap pad?
>
> I've seen app notes state either of these ways. My
> consideration is if via is at decap pad, then there is more
> inductance to device resulting in more noise in device (e.g.
> ground bounce). If via is at device pin, then there is more
> inductance to decap, resulting in more noise on plane.
>
> Looking for insight here. Comments?
>
> Thanks,
>
> Ivor
>
>
>
>
>
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