[SI-LIST] Re: understanding acceptable amount of jitter for given receiver/system
- From: "Jory McKinley" <dmarc-noreply@xxxxxxxxxxxxx> (Redacted sender "jory_mckinley@xxxxxxxxx" for DMARC)
- To: "ajay.dhingra@xxxxxxxxx" <ajay.dhingra@xxxxxxxxx>
- Date: Mon, 1 Sep 2014 10:50:43 -0700
Hello Ajay,
There are several approaches to incorporating Jitter analysis for your channel
into your simulations which are pretty much standard, see Hspice manual, or
industry simulation tool manual. I would recommend and most cases you may not
have a choice but build a TX/RX model that incorporates the channel Jitter
specifications directly into the behavioral model (Spice, IBIS-AMI..). Once
and if you acquire the actual PHY specifications for Jitter and other
electrical characteristics you can build these into your behavioral model.
As far as test patterns to apply for your channel each standard has some
variation of the type of pattern and duration. In general a standard PRBS
pattern run for 1M bits will get you through most your standard compliance
requirements. You can use PDA (peak distortion analysis) or Statistical
analysis in some cases and this will tend to converge very long PRBS runs.
If you need help on more specific channel methodology/requirements we might
want to take off line.
Regards,
-Jory
On Sunday, August 31, 2014 3:24 AM, Ajay Dhingra <ajay.dhingra@xxxxxxxxx> wrote:
Hi Jory
Could you please explain, how to incorporate/embed jitter profile into the
hspice model of Transmitter to simulate and verify BER compliance. Does it
require any information to be provided by PHY vendor in terms of Jitter
profile PWL or it will be standard procedure based upon Jitter Vectors.
Pls forward me some documents which defines the essential checks to sign
off a Differential interface in Simulation.
Thanks and Regards
Ajay
On Fri, Aug 29, 2014 at 11:19 PM, Jory McKinley <jory_mckinley@xxxxxxxxx>
wrote:
> Ajay/Eric,
> You can test the receiver in simulation land which if done correctly can
> be used to correlate laboratory compliance. If you have accurate model (
> IBS-AMI, Behavioral, Spice) of your TX and RX with the associated jitter
> profile and equalizer settings then you should be able to simulate the
> required pattern(s) to achieve your Serdes required BER mask. This is
> refereed to as a full channel simulation and you will never apply anywhere
> near 1UI of correlated or uncorrelated jitter to the full channel
> simulation.
> Where the 1UI and many multiples higher and lower come into play in the
> Serdes specs is when you run an RX Jitter tolerance test which is done
> with a swept sinusoidal sweep Jitter source applied to the RX in some sort
> of loop back. The idea is to test the CDR bandwidth of the RX this can be
> done in simulation but is simulated outside the designed channel.
> Tons of information from many sources Agilent, Tektronix, and so on.
> Regards,
> -Jory
>
>
> On Friday, August 29, 2014 8:26 AM, Ajay Dhingra <ajay.dhingra@xxxxxxxxx>
> wrote:
>
>
> Hi Eric:
> 1UI jitter should be correlated jitter in my opinion. CDR at Rx side should
> generally track this much high jitter, though actual limits depends upon
> implementation. Hence if it's tracked by PLL and CDR both then it shouldn't
> really cause a bit error. In BER simulation i think only uncorrelated
> jitter should be taken into consideration.
>
> Thanks
> Ajay
>
>
> On Fri, Aug 29, 2014 at 2:53 AM, eric silist <ericsilist@xxxxxxxxx> wrote:
>
> > Hi all,
> > I'm having trouble trying to understand how to define what an
> > acceptable amount of jitter would be for my serial link. I imagine this
> > is very broad question but I'm trying to wrap my head around the
> basics. I
> > have an ibis model for my transmitter and receiver and I've hooked them
> up
> > in spice along with an s-parameter model of my channel. I was pretty
> happy
> > with myself that I got this part to work :)
> > Then I get some outputs that I'm used to looking at, eye diagram, ber
> > contour, bathtub. I can play with settings in the model and get more
> open
> > or closed eyes. So that was fun.
> >
> > Then I thought how do I tell, and tell someone else whether this data we
> > are looking at is good enough to meet our target BER or not? For
> voltage I
> > went into the serdes datasheet and saw that it was adjustable but the
> > threshold voltage for signal detect was say 50mV diff. So then I believe
> > that as long as over 1E-12 bits, my lowest vertical eye opening is not
> > lower than 50mV diff then that would be acceptable. I'm sure some margin
> > would also be nice.
> >
> > Next I wanted to understand the same thing for jitter. I started by
> > looking at the bathtub curve at 1E-12 which I think is just telling me,
> "if
> > you ran 1E-12 bits, based on probability this is the eye opening you
> would
> > see".
> >
> > My question is how do I relate this data back to the receiver
> > requirements/spec to decide if it looks good or not? I think I
> understand
> > that what can screw the receiver up would be the clock recovery circuit
> to
> > lose it's lock. There is one spec in the receiver that says total
> receive
> > input jitter can be 1UI-pkpk. That seems really high though since I'd
> > think that would mean the eye was completely closed.
> >
> > Anyway I'm a little stuck, I've tried to do some reading and I've found
> > lots about what a bathtub curve is, what jitter is etc, but nothing so
> far
> > that ties it back to the real world for me. I guess in the past it's
> > always been defined for me by the spec, but now I find myself wanting to
> > understand more about it.
> >
> > Thank you,
> > -Eric
> >
> >
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>
>
> --
> AJAY DHINGRA
> Bangalore, India
> 9741414027
> It is Attitude,Not Aptitude, that determines your Altitude.
>
>
>
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--
AJAY DHINGRA
Bangalore, India
9741414027
It is Attitude,Not Aptitude, that determines your Altitude.
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