[SI-LIST] Re: the most desirable power plane design scheme
- From: steve weir <weirsi@xxxxxxxxxx>
- To: jemanakk@xxxxxxxxxxxxxxxxxxx
- Date: Wed, 31 Mar 2010 07:20:16 -0700
Joseph there is no generic correct answer. The starting point is to
translate the requirements into an impedance versus frequency required
at each of the big ICs. Then sit down and start to evaluate your
alternatives, keeping in mind what else the PCB has to do. Good
engineering practice would tell you to address the PCB design beginning
with the most restrictive requirement first.
The more commonality / fewer power nets you have the fewer components
that will be required. Isolation techniques like ferrite beads are very
powerful, but they come at a price. Many people have abused ferrite
beads to the point where they would have been much better off without
them in the first place. If you want to learn more about ferrite beads
and how to use them properly:
http://www.ipblox.com/pubs/Ferrite_beads/Understanding%20Ferrite%20Beads%20and%20Applications.pdf
My basic message is to isolate where it provides you an advantage that
justifies the additional parts required.
If you have ground loops in a high frequency PCB something is
disastrously wrong. The closest thing you should have to a ground loop
is a Vss-Vss or Vss- case cavity resonance and with proper stitching the
lowest modal frequency should be well out of the way of any significant
signal components that could excite the cavity. See Doug Smith's
www.emcesd.com web site for more information about PCB to case
resonances. Doug has started up a paid site circuitadvisor.com where he
is migrating the wealth of information he has developed.
Steve.
jemanakk@xxxxxxxxxxxxxxxxxxx wrote:
> Hi,
> Thanks for all excellent feedbacks for the coupling cap and power plane
> design.
>
>
> I have another question related to one of my present design:
>
> A board design with 2 FPGA, 5 processors, 3 set of DDR2 DRAM, Gbit
> Ethernets, USB2.0HS, etc.
> There are many voltages common for Processors, FPGAs, PHYs, etc.
>
> What should be the most desirable power plane design scheme?
>
> 1. Dedicated (power islands, isolated by ferrite beads from the common
> power grid/plane) power for each processor, DDR2s, FPGAs etc?
>
> 2. Common power plane for devices with similar voltage (for example: one
> core-voltage-power plane for all processors)?
>
> 3. How much ground-loops and switching noise needs to be considered/worry
> in a multi processor/FPGA/PHYs/DDR2s/etc design on a single board? Is
> there any simplified (rule-of-thumb) board level analysis?
> (Note: I always use HyperLynx based SI analysis for board design, for all
> critical signal routing).
>
> Best regards,
> Joseph
>
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--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
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