[SI-LIST] Re: the most desirable power plane design scheme
- From: jemanakk@xxxxxxxxxxxxxxxxxxx
- To: wjcsongr@xxxxxxxxxxxxxxxxxxx, List Si <si-list@xxxxxxxxxxxxx>
- Date: Wed, 31 Mar 2010 10:56:19 -0500
Content-Type: text/plain; charset="US-ASCII"
Hi to All,
Thanks for all discussions about power plane design schemes.
I agree with most of feedbacks, that is why I presented two common power
plane design scenarios.
I do believe: there is no perfection is any design, a practical design
goal is only a compromise between limits of perfection and limits of
acceptance (per design requirements).
Sorry for the short answer:
- Usually I select ferrite bead (if needed), per the max-clock
frequency/max-switching frequency, power requirements and nature of the
device/design of interest.
- If Power Island created for a specific device, it is very much assumed
as if running from its own independent power supply (with enough bulk and
decoupling caps used after ferrite bead).
Best regards,
Joseph
--------------------
Please see the following interesting ferrite bead analysis:
I could not find the original source of this analysis (I will post once I
get the original doc/source)
--------------------------------------------------------------------------
William J Csongradi Jr/CedarRapids/RockwellCollins
03/31/2010 09:44 AM
To
steve weir <weirsi@xxxxxxxxxx>
cc
Istvan Novak <istvan.novak@xxxxxxx>, jemanakk@xxxxxxxxxxxxxxxxxxx
Subject
Re: [SI-LIST] Re: the most desirable power plane design scheme
Whole heartedly agree. However, since Joe is also a Rockwell guy, he can
verify that beads are used in a lot of applications inappropriately, here
at the Rock, no question.
I've seen way too many designs here, not so much at IBM, where not only
are there ferrites everywhere, but they're exactly the SAME part
number...how can that be unless following the 'rule of thumb' to put on a
bead? How can you apply a bead without knowing your frequency of interest!
Here's a real live example. Cypress had this clock device that we were
using at IBM. The EE INSISTED that we needed a bead on that thing and he
wasn't going to change his mind. Well, we finally called Cypress and had a
discussion, and the clock chip was sensitive to 5-10 MHZ. Anything higher
than that was a don't care. So, using a 100 Ohm bead (at 100 Mhz) wasn't
going to buy us anything. So we went with my preferred filter, an RC
filter, designed for -3dB (at least) at the lowest frequency of interest.
Worked great. Also, some extensive study was done at IBM on PLL ferrite
beads and what the geniuses finally came up with was putting a 1 Ohm in
series with the bead to 'dampen resonances'...well, I say, toss the bead
and just use the resistor. But what do I know: - )
Regards,
Bill
William Csongradi
Senior Electrical Engineer
Rockwell Collins Heads Down Display Center
319-295-7884
Mailing Address
Rockwell Collins
400 Collins Road NE
MS 105-167
Cedar Rapids, Iowa 52498-0001
steve weir <weirsi@xxxxxxxxxx>
03/31/2010 09:31 AM
To
wjcsongr@xxxxxxxxxxxxxxxxxxx
cc
Istvan Novak <istvan.novak@xxxxxxx>, jemanakk@xxxxxxxxxxxxxxxxxxx
Subject
Re: [SI-LIST] Re: the most desirable power plane design scheme
Bill, ferrite beads gained a reputation as a magical fix for EMC
problems decades ago. What people often miss is that the original
application for ferrite beads was in decoupling narrow band RF amplifier
stages, where used properly they excel. However, as long as I have been
in the business people have been sticking them in places they don't
belong, or using them without taking the other necessary measures
required for them to do their job without bad side effects such as
starving out an IC they feed. In other cases, people have been so
burned by misapplication that they won't consider them, even when they
offer an elegant and powerful solution.
Choose ferrite bead application wisely, and choose the right bead for
the application.
Best Regards,
Steve.
wjcsongr@xxxxxxxxxxxxxxxxxxx wrote:
>
> Let me ask a dumb question...what is with this fascination with
> ferrite beads? Why would you isolate the chips?
>
> Except for maybe Intel, data sheets will say put a ferrite bead here
> or there. But they usually don't specify the frequency range of the
> bead, etc. If you don't design with a frequency range of interest in
> mind, how can just tossing any old bead on help? What if that bead
> chokes off the switching current (assuming you didn't put any decaps
> on the other side of the bead...hey, I've seen it many times)? If you
> charge starve your device, that obviously will cause problems.
>
> So, how do you experts decide 1. Do you isolate with beads. 2. How do
> you determine the frequencies of interest that you wish to block/filter?
>
> For some switching cores, you may be in the amps of current. That's a
> pretty physically large bead, no?
>
> Regards,
>
> Bill
>
> William Csongradi
> Senior Electrical Engineer
> Rockwell Collins Heads Down Display Center
> 319-295-7884
>
> Mailing Address
> Rockwell Collins
> 400 Collins Road NE
> MS 105-167
> Cedar Rapids, Iowa 52498-0001
>
>
>
>
> *Istvan Novak <istvan.novak@xxxxxxx>*
> Sent by: si-list-bounce@xxxxxxxxxxxxx
>
> 03/31/2010 08:26 AM
>
>
> To
> jemanakk@xxxxxxxxxxxxxxxxxxx
> cc
> List Si <si-list@xxxxxxxxxxxxx>
> Subject
> [SI-LIST] Re: the most desirable power plane design
scheme
>
>
>
>
>
>
>
>
>
> Hi Joseph,
>
> As always, the answer depends on several additional factors.
>
> In your case it may depend on:
> - what are (if any) restrictions you have on the board? (shape, size,
> thickness, component placement)
> - what is the total current if you combine rails (painfully high or
> still reasonable)
>
> Within a large range of parameter sets you should be able to make it
> either way, and the answer would depend on these additional factors.
>
> Regards,
>
> Istvan Novak
> Oracle-Sun
>
>
>
>
> jemanakk@xxxxxxxxxxxxxxxxxxx wrote:
> > Hi,
> > Thanks for all excellent feedbacks for the coupling cap and power
plane
> > design.
> >
> >
> > I have another question related to one of my present design:
> >
> > A board design with 2 FPGA, 5 processors, 3 set of DDR2 DRAM, Gbit
> > Ethernets, USB2.0HS, etc.
> > There are many voltages common for Processors, FPGAs, PHYs, etc.
> >
> > What should be the most desirable power plane design scheme?
> >
> > 1. Dedicated (power islands, isolated by ferrite beads from the common
> > power grid/plane) power for each processor, DDR2s, FPGAs etc?
> >
> > 2. Common power plane for devices with similar voltage (for example:
> one
> > core-voltage-power plane for all processors)?
> >
> > 3. How much ground-loops and switching noise needs to be
> considered/worry
> > in a multi processor/FPGA/PHYs/DDR2s/etc design on a single board? Is
> > there any simplified (rule-of-thumb) board level analysis?
> > (Note: I always use HyperLynx based SI analysis for board design,
> for all
> > critical signal routing).
> >
> > Best regards,
> > Joseph
> >
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--
Steve Weir
IPBLOX, LLC
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