[SI-LIST] the most desirable power plane design scheme
- From: jemanakk@xxxxxxxxxxxxxxxxxxx
- To: List Si <si-list@xxxxxxxxxxxxx>
- Date: Wed, 31 Mar 2010 01:49:58 -0500
Hi,
Thanks for all excellent feedbacks for the coupling cap and power plane
design.
I have another question related to one of my present design:
A board design with 2 FPGA, 5 processors, 3 set of DDR2 DRAM, Gbit
Ethernets, USB2.0HS, etc.
There are many voltages common for Processors, FPGAs, PHYs, etc.
What should be the most desirable power plane design scheme?
1. Dedicated (power islands, isolated by ferrite beads from the common
power grid/plane) power for each processor, DDR2s, FPGAs etc?
2. Common power plane for devices with similar voltage (for example: one
core-voltage-power plane for all processors)?
3. How much ground-loops and switching noise needs to be considered/worry
in a multi processor/FPGA/PHYs/DDR2s/etc design on a single board? Is
there any simplified (rule-of-thumb) board level analysis?
(Note: I always use HyperLynx based SI analysis for board design, for all
critical signal routing).
Best regards,
Joseph
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
