[SI-LIST] Re: termination for routing 8 SDRAMs to single P rocessor
- From: "Peterson, James F (FL51)" <james.f.peterson@xxxxxxxxxxxxx>
- To: scott@xxxxxxxxxxxxx, david.novak@xxxxxxxxxxx
- Date: Thu, 11 Aug 2005 09:51:42 -0700
David,
Please reply to all if you find one of these "well documented" write-ups. A
quick tour of Scott's link revealed little. A lot of the links were related
to ESD and overstress caused by large slow overshoots. I could have missed
something - only a quick look.
(I would like to understand better (details / physics) why I have stay
within those bloody AC overshoot & undershoot thresholds.)
Jim
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Scott McMorrow
Sent: Thursday, August 11, 2005 11:39 AM
To: david.novak@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor
Try this application note by Freescale
The Google search was: Semiconductor input overstress
http://www.google.com/search?hl=en&q=semiconductor+input+overstress&btnG=Goo
gle+Search
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed(r) is the registered service mark of Teraspeed Consulting Group
LLC
Novak David (TTE) wrote:
>"Overstress damage from repeated excess overshoot is a well documented
>phenomenon."
>
>Can you please point me in the direction of this documentation. My web
>search was fruitless.
>
>Thanks,
>David=20
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of steve weir
>Sent: Thursday, August 11, 2005 3:59 AM
>To: dp@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: termination for routing 8 SDRAMs to single
>Processor
>
>Dimiter, I am sorry you find this thread so upsetting. If it appears
>that I have assaulted your skills, it was certainly not my intention to
>do so.
>
>Overstress damage from repeated excess overshoot is a well documented
>phenomenon. It doesn't mean that your design unknowingly suffered from
>it. I don't know if it did or did not. IF excessive overshoot was
>present and you still observed no failure then, yes I side up with Ken
>in the view that you were lucky. But, if you had enough margin, then
>there was no need for luck. I don't know. I was trying to find out.
>I am sorry it upset you.
>
>Steve.
>
>At 10:50 AM 8/11/2005 +0300, Dimiter Popoff wrote:
>
>
>>>Dimiter, as we just finished discussing, the I/Os on the 8420 may be
>>>
>>>
>
>
>
>>>considerably more robust than on other parts.
>>>
>>>
>>Oh may be they are and may be they are not.
>>Just as there may be an end of time and then may be there is none.
>>
>>
>>
>>> We also never established what kind of overshoot you had.
>>>
>>>
>>"We" did not. I decided 5 years ago there would be no issues, and I=20
>>proved right.
>>
>>The product was never meant for what you would call mass production,
>>I=20 admit I would have been more conservative if this had been
anticipated.
>>It will never go in the thousands of units, so some of the pro=20
>>overdesign arguments you put forward are valid.
>> But please don't give me that "you can't know because I don't"=20
>>because it is not true. I can know and I do know when I design
>>
>>
>something.
>
>
>>I have more entire projects behind me than I care to think of and=20
>>you'll have to work for another while on the details if you want to=20
>>call me lucky. The while may be longer than a lifetime.
>>
>>Now I am going out for a walk and _this_ is the last on that thread
>>I=20 post, this is a promise to the rest of the listmembers who are
>>probably
>>
>>
>
>
>
>>fed up with the thing already - and I only wanted to share
>>experience,=20 see my first message.
>>
>>Dimiter
>>
>>------------------------------------------------------
>>Dimiter Popoff Transgalactic Instruments
>>
>>http://www.tgi-sci.com
>>------------------------------------------------------
>>
>>
>>
>>
>>-------Original Message-------
>>
>>
>>>From: steve weir <weirsi@xxxxxxxxxx>
>>>Subject: Re: [SI-LIST] Re: termination for routing 8 SDRAMs to
>>>
>>>
>>single Processor
>>
>>
>>>Sent: Aug 11 '05 10:23
>>>
>>> Dimiter, as we just finished discussing, the I/Os on the 8420 may=20
>>>be considerably more robust than on other parts. We also never=20
>>>established what kind of overshoot you had.
>>>
>>> The problems caused by overshoot on modern silicon are well
>>>
>>>
>documented.
>
>
>>> Dr. Deming would not be happy with your conclusion that a single=20
>>>unit sample predicts what a larger population will do. Before we
>>>
>>>
>can gainfully
>
>
>>> use a sample, we need to know what our variations are. This is
>>>
>>>
>no=20
>
>
>>slight
>>
>>
>>> against you, it is just the tyranny of SPC.
>>>
>>> Steve.
>>> At 10:07 AM 8/11/2005 +0300, Dimiter Popoff wrote:
>>> >So you have seen many prototypes which operated continuously >for
>>>
>>>
>
>
>
>>>about 4 years and exhibit problems once they go into mass
>>>
>>>
>production.
>
>
>>> >Well, kucky me. I had no problems.
>>> >
>>> >Dimiter
>>> >
>>> >------------------------------------------------------
>>> >Dimiter Popoff Transgalactic Instruments
>>> >
>>> >http://www.tgi-sci.com
>>> >------------------------------------------------------
>>> >
>>> >
>>> >
>>> >
>>> >-------Original Message-------
>>> > > From: Kenneth W. Egan <kegan@xxxxxxxxxxxxx> > > Subject: RE:=20
>>>[SI-LIST] Re: termination for routing 8 SDRAMs to single >=20
>>>Processor > > Sent: Aug 11 '05 09:47 > >
>>> > > ??
>>> > > Depends upon the characterization of the silicon on both
>>>
>>>
>sides.=20
>
>
>>So it's a
>>
>>
>>> > > statistics thing. How many units have you shipped ? This is=20
>>>the > determining > > factor, not one unit for a period of time.
>>> > >
>>> > > Overshoot is an issue for many silicon vendors. For example,=20
>>>one
>>>
>>>
>>of TI's
>>
>>
>>> > > DSP's call out max of 4.3v overshoot for 3.3v I/O on their=20
>>>SDRAM
>>>
>>>
>>I/F. But
>>
>>
>>> > > the real piece is the spec that indicates, not only 4.3v,
>>> > > but=20
>>>also > only over > > a max of 30% of the clock period. So this=20
>>>may indicate junction > > heating/oxide breakdown issues with
>>>the=20 process node, or design
>>>
>>>
>>of their
>>
>>
>>> > > device.
>>> > >
>>> > > I've seen plenty of prototypes that work fine, put them in=20
>>>mass > production, > > and these issues start cropping up.
>>> > >
>>> > > KWE
>>> > >
>>> > > -----Original Message-----
>>> > > From: Dimiter Popoff [mailto:dp@xxxxxxxxxxx] > > Sent:=20
>>>Thursday, August 11, 2005 12:56 AM > > To: Kenneth W. Egan;=20
>>>aavinda12@xxxxxxxxx; si-list@xxxxxxxxxxxxx > > Subject: RE:=20
>>>[SI-LIST] Re: termination for routing 8 SDRAMs to single > > =20
>>>Processor > > > > Is about 4 years practically continuous=20
>>>operation good enough?
>>> > > The design has demonstrated it.
>>> > >
>>> > > Dimiter
>>> > >
>>> > > ------------------------------------------------------
>>> > > Dimiter Popoff Transgalactic Instruments
>>> > >
>>> > > http://www.tgi-sci.com
>>> > > ------------------------------------------------------
>>> > >
>>> > >
>>> > >
>>> > >
>>> > > -------Original Message------- > > > From: Kenneth W. Egan=20
>>><kegan@xxxxxxxxxxxxx> > > > Subject: RE: [SI-LIST] Re: termination
>>>
>>>
>
>
>
>>>for routing 8 SDRAMs to
>>>
>>>
>>single
>>
>>
>>> > > > Processor
>>> > > > Sent: Aug 11 '05 05:21
>>> > > >
>>> > > > The question might not be one of stability, but one of
>>>
>>>
>>reliability in
>>
>>
>>> > > > the long term. Sure, you'll probably meet setup and hold
>>>
>>>
>>to/from the
>>
>>
>>> > > SDRAM.
>>> > > > However, SDRAM typically has some pretty hot drivers (that
>>>
>>>
>>I've seen,
>>
>>
>>> > > > simulated and measured in circuit ) and the real issue is=20
>>>over > > > stressing The input protection on the receiver, i.e.=20
>>>overshoot
>>>
>>>
>>issues.
>>
>>
>>> > > >
>>> > > > Failure modes in this case may not occur until much later
>>>
>>>
>in time.
>
>
>>> > > >
>>> > > > KWE
>>> > > >
>>> > > >
>>> > > > -----Original Message-----
>>> > > > From: si-list-bounce@xxxxxxxxxxxxx > > >=20
>>>[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Dimiter Popoff
>>>=20
>>>
>>>
>>>>> > Sent: Wednesday, August 10, 2005 8:00 PM > > > To:=20
>>>>>
>>>>>
>>>aavinda12@xxxxxxxxx; si-list@xxxxxxxxxxxxx > > > Subject:=20
>>>[SI-LIST] Re: termination for routing 8 SDRAMs to single > > >=20
>>>Processor > > > > > > I have rooted 8 x8 SDRAMs to an 8240=20
>>>without any terminations
>>>
>>>
>>and it
>>
>>
>>> > > > worked remarkably stable. However, I had 64 data bits=20
>>>rather
>>>
>>>
>>than 32.
>>
>>
>>> > > > I had put 4 SDRAM chips on top and 4 on the bottom of the=20
>>>board, > > > practically next to the CPU, no connectors between.
>>> > > >
>>> > > > Dimiter
>>> > > >
>>> > > > ------------------------------------------------------
>>> > > > Dimiter Popoff Transgalactic Instruments
>>> > > >
>>> > > > http://www.tgi-sci.com
>>> > > > ------------------------------------------------------
>>> > > >
>>> > > >
>>> > > >
>>> > > >
>>> > > > -------Original Message------- > > > > From: Aravnda G=20
>>><aavinda12@xxxxxxxxx> > Subject: [SI-LIST] > > > termination
>>>for=20 routing 8 SDRAMs to single > Processor >
>>>
>>>
>>Sent: Aug
>>
>>
>>> > > > 11 '05 03:29 > > Hi All, > I am working with a=20
>>>micro-processor > > > conneted to 8 SDRAM with 12 address lines=20
>>>to all SDRAMs and 32
>>>
>>>
>>data
>>
>>
>>> > > > lines each to two sets of four SDRAMs. I was wondering if
>>>
>>>
>>anyone has
>>
>>
>>> > > > managed to route this sort of topology without
>>>
>>>
>>using terminations. If
>>
>>
>>> > > > so please send information on topology used. The IO are =20
>>>lvttl > > > compatible at 3.3V. Any input on routing possibilities
>>>
>>>
>is welcome.
>
>
>>> > > > >
>>> > > > > Thanks & Regards,
>>> > > > > Alex.
>>> > > > >
>>> > > > > --------------------------------- > > > > Yahoo!=20
>>>Mail > > > > Stay connected, organized, and protected. Take
>>>the=20 tour > > > > >=20
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>>-------Original Message-------
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Other related posts:
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