[SI-LIST] Re: tDQSCK
- From: "Fraiman, Edi" <Edi.Fraiman@xxxxxxxxxx>
- To: "Jory McKinley" <jory_mckinley@xxxxxxxxx>, <james.f.peterson@xxxxxxxxxxxxx>, "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 31 Oct 2006 15:47:45 -0500
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Jory,
=20
I am speaking about DQS width.
tDQSCK parameter defined as "DQS output access time from CK/~CK "
(usually min. -0.6ns and max. 0.6ns).
If DDR clock is 200Mhz than clock cycle is 5ns and half cycle is 2.5ns,
then DQS width could be 2.5-0.6+(-0.6) =3D 1.3 ns.
Please see in attached data sheet p.80 Figure 42: Data Output Timing -
tAC and tDQSCK. The DQS could be wide and thin, so tDQSCK is a jitter.
=20
Best regards,
Edi Fraiman
=20
=20
=20
-----Original Message-----
From: Jory McKinley [mailto:jory_mckinley@xxxxxxxxx]=20
Sent: Tuesday, October 31, 2006 3:33 PM
To: Fraiman, Edi; james.f.peterson@xxxxxxxxxxxxx; si-list
Subject: Re: [SI-LIST] Re: tDQSCK
=09
=09
Edi,
For Read timing the relationship to consider is the DQ to DQS
skew from the memory which is roughly +/- 400ps for this part. If you
are running at 200Mhz as you mentioned the window to hit will be 2.5ns.
This leaves you with about 1.7ns to account for the controller DQ/DQS
setup/hold time as well as the min/max flight time variation between
DQ/DQS. Hope this is helpful,
-Jory
=09
"Fraiman, Edi" <Edi.Fraiman@xxxxxxxxxx> wrote:=20
Jim,
=09
Yes you are correct I am speaking about read cycle for
DDR1.
If my calculations below are right I do not understand
how DDR
controller could face such tight number as 1.3ns.
------------------------
Lets say that DDR clock is 200Mhz so clock cycle is 5ns
and half cycle
is 2.5ns.
=09
According to DDR1 data sheet tDQSCK (DQS output access
time from CK/~CK
) is -0.6ns min. and +0.6ns max.
=09
Then DQS width could be 2.5-(0.6+0.6) =3D3D 1.3 ns.
--------------------------------
=3D20
Best regards,
Edi Fraiman
=3D20
=3D20
=3D20
=09
=09
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=3D20
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of
Peterson,=3D20
> James F (EHCOE)
> Sent: Tuesday, October 31, 2006 7:43 AM
> To: si-list
> Subject: [SI-LIST] Re: tDQSCK
>=3D20
>=3D20
> Edi,
>=3D20
> Although DQS can occur before CK, tDQSCK is not
really=3D20
> jitter. In other words it's not a cycle by cycle
variant -=3D20
> more a long term delay. So it's shifts, but doesn't
"shrink".
>=3D20
> I assume this is a read cycle (since you're looking at
the=3D20
> DDR driving DQS). Isn't the most important timing the
delay=3D20
> between DQS and DQ? And this is not directly
influenced by=3D20
> tDQSCK. (only indirectly when you cross clock domains
back at=3D20
> the controller during a read cycle.)=3D3D20
>=3D20
> If I'm correct in my above assumption then you are
indeed=3D20
> seeing a timing violation. And you should. DDR SDRAM
does not=3D20
> put DQS in the middle of the DQ "eye". You have to do
it=3D20
> either in the controller or on the pcb.=3D3D20
>=3D20
> DDR SDRAM is very spoiled : it insists that during a
write=3D20
> cycle that the controller takes care of tSU/tHOLD
between DQS=3D20
> and DQ and during a read cycle, as it outputs DQS and
DQ, it=3D20
> makes the same demand.
>=3D20
> (a word of caution, my reply is very relative to DDR1,
I'm=3D20
> not absolutely sure about DDR2)=3D3D20
>=3D20
> Jim Peterson
> Honeywell
>=3D20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=3D20
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Fraiman, Edi
> Sent: Monday, October 30, 2006 2:44 PM
> To: si-list
> Subject: [SI-LIST] tDQSCK
>=3D20
> Content-Type: text/plain; charset=3D3D3D"us-ascii"
> Content-Transfer-Encoding: quoted-printable Hi,=3D3D3D20
>=3D20
> I have question about Micron DDR parameter
tDQSCK=3D3D3D3DAccess=3D20
> window of =3D3D DQS from CK/CK#.=3D3D3D20 According Micron
data sheet=3D20
> this time is jitter and =3D3D not skew.=3D3D3D20
>=3D20
> =3D3D3D20
> Please see the diagram from Micron data sheet : the
DQS=3D20
> signal could be wider or thinner because max. and min.
of tDQSCK.
>=3D20
> But according to JEDEC JESD79E tDQSCK is skew from
CK/CK# =3D20
> and DQS could not be wider or thinner please see
below=3D20
> diagram from JEDEC.
>=3D20
> =3D3D3D20
> The problem is when I prepare timing diagrams with=3D20
> TimingDesigner tool if I assume than tDQSCK is jitter
from=3D20
> CK/CK# and DQS could be wider or thinner than I get
time violation.
>=3D20
> If I assume than tDQSCK is skew from CK/CK# and DQS
could=3D20
> not be wider or thinner than timing is OK.=3D3D3D20
>=3D20
>=3D20
>=3D20
>=3D20
> Best regards,
> Edi Fraiman
>=3D20
>=3D20
>=3D20
>=3D20
>=3D20
>=3D20
>=3D20
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