[SI-LIST] Re: tDQSCK
- From: "Fraiman, Edi" <Edi.Fraiman@xxxxxxxxxx>
- To: <james.f.peterson@xxxxxxxxxxxxx>, "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 31 Oct 2006 08:49:02 -0500
Jim,
Yes you are correct I am speaking about read cycle for DDR1.
If my calculations below are right I do not understand how DDR
controller could face such tight number as 1.3ns.
------------------------
Lets say that DDR clock is 200Mhz so clock cycle is 5ns and half cycle
is 2.5ns.
According to DDR1 data sheet tDQSCK (DQS output access time from CK/~CK
) is -0.6ns min. and +0.6ns max.
Then DQS width could be 2.5-(0.6+0.6) =3D 1.3 ns.
--------------------------------
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Best regards,
Edi Fraiman
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> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=20
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Peterson,=20
> James F (EHCOE)
> Sent: Tuesday, October 31, 2006 7:43 AM
> To: si-list
> Subject: [SI-LIST] Re: tDQSCK
>=20
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> Edi,
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> Although DQS can occur before CK, tDQSCK is not really=20
> jitter. In other words it's not a cycle by cycle variant -=20
> more a long term delay. So it's shifts, but doesn't "shrink".
>=20
> I assume this is a read cycle (since you're looking at the=20
> DDR driving DQS). Isn't the most important timing the delay=20
> between DQS and DQ? And this is not directly influenced by=20
> tDQSCK. (only indirectly when you cross clock domains back at=20
> the controller during a read cycle.)=3D20
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> If I'm correct in my above assumption then you are indeed=20
> seeing a timing violation. And you should. DDR SDRAM does not=20
> put DQS in the middle of the DQ "eye". You have to do it=20
> either in the controller or on the pcb.=3D20
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> DDR SDRAM is very spoiled : it insists that during a write=20
> cycle that the controller takes care of tSU/tHOLD between DQS=20
> and DQ and during a read cycle, as it outputs DQS and DQ, it=20
> makes the same demand.
>=20
> (a word of caution, my reply is very relative to DDR1, I'm=20
> not absolutely sure about DDR2)=3D20
>=20
> Jim Peterson
> Honeywell
>=20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=20
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Fraiman, Edi
> Sent: Monday, October 30, 2006 2:44 PM
> To: si-list
> Subject: [SI-LIST] tDQSCK
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> Content-Type: text/plain; charset=3D3D"us-ascii"
> Content-Transfer-Encoding: quoted-printable Hi,=3D3D20
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> I have question about Micron DDR parameter tDQSCK=3D3D3DAccess=20
> window of =3D DQS from CK/CK#.=3D3D20 According Micron data sheet=20
> this time is jitter and =3D not skew.=3D3D20
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> =3D3D20
> Please see the diagram from Micron data sheet : the DQS=20
> signal could be wider or thinner because max. and min. of tDQSCK.
>=20
> But according to JEDEC JESD79E tDQSCK is skew from CK/CK# =20
> and DQS could not be wider or thinner please see below=20
> diagram from JEDEC.
>=20
> =3D3D20
> The problem is when I prepare timing diagrams with=20
> TimingDesigner tool if I assume than tDQSCK is jitter from=20
> CK/CK# and DQS could be wider or thinner than I get time violation.
>=20
> If I assume than tDQSCK is skew from CK/CK# and DQS could=20
> not be wider or thinner than timing is OK.=3D3D20
>=20
>=20
>=20
>=20
> Best regards,
> Edi Fraiman
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