[SI-LIST] Re: tDQSCK
- From: "Peterson, James F \(EHCOE\)" <james.f.peterson@xxxxxxxxxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 31 Oct 2006 06:43:05 -0600
Edi,
Although DQS can occur before CK, tDQSCK is not really jitter. In other
words it's not a cycle by cycle variant - more a long term delay. So
it's shifts, but doesn't "shrink".
I assume this is a read cycle (since you're looking at the DDR driving
DQS). Isn't the most important timing the delay between DQS and DQ? And
this is not directly influenced by tDQSCK. (only indirectly when you
cross clock domains back at the controller during a read cycle.)=20
If I'm correct in my above assumption then you are indeed seeing a
timing violation. And you should. DDR SDRAM does not put DQS in the
middle of the DQ "eye". You have to do it either in the controller or on
the pcb.=20
DDR SDRAM is very spoiled : it insists that during a write cycle that
the controller takes care of tSU/tHOLD between DQS and DQ and during a
read cycle, as it outputs DQS and DQ, it makes the same demand.
(a word of caution, my reply is very relative to DDR1, I'm not
absolutely sure about DDR2)=20
Jim Peterson
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Fraiman, Edi
Sent: Monday, October 30, 2006 2:44 PM
To: si-list
Subject: [SI-LIST] tDQSCK
Content-Type: text/plain; charset=3D"us-ascii"
Content-Transfer-Encoding: quoted-printable Hi,=3D20
I have question about Micron DDR parameter tDQSCK=3D3DAccess window of =
DQS
from CK/CK#.=3D20 According Micron data sheet this time is jitter and =
not
skew.=3D20
=3D20
Please see the diagram from Micron data sheet : the DQS signal could be
wider or thinner because max. and min. of tDQSCK.
But according to JEDEC JESD79E tDQSCK is skew from CK/CK# and DQS
could not be wider or thinner please see below diagram from JEDEC.
=3D20
The problem is when I prepare timing diagrams with TimingDesigner tool
if I assume than tDQSCK is jitter from CK/CK# and DQS could be wider
or thinner than I get time violation.
If I assume than tDQSCK is skew from CK/CK# and DQS could not be wider
or thinner than timing is OK.=3D20
Best regards,
Edi Fraiman
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