[SI-LIST] Re: split plane
- From: Shelesh Somani <shelesh@xxxxxxxxx>
- To: Nitin.Sood@xxxxxxx, weirsi@xxxxxxxxxx
- Date: Thu, 21 Apr 2005 10:42:47 +0530
Nitin,
First of all as Steve mentioned you need to copper balance your
stack-up. The best you can do by having Ground /Power plane + Signal
on S1.
Now coming to your query. If Synchronous data bus is running over
split, there should be a a good de-coupling between the planes (on
which traces are crossing the split) to provide return path. You can
do this by putting de-caps between both the planes near splits.
But I see one more issue in the satck-up: S1 traces may have cross
talk with S2 traces if they are overlapping each other. That should be
taken care.
Shelesh=20
On 4/12/05, steve weir <weirsi@xxxxxxxxxx> wrote:
> Nitin, Sa, Sb, S2, and Sd are suitable to high edge rate signals. P and
> S1 need to be copper balanced. S1 only has return path to the extent tha=
t
> signals match copper on P. The best that I could recommend would be to
> weave power / ground / signals on P and S1 rather than trying to place
> power only on P.
>=20
> Steve
>=20
> At 01:41 PM 4/11/2005 -0700, Nitin Sood wrote:
>=20
> >Hi Doug,
> >
> >The total board thickness is ~ 60 mills and with the following =3D
> >dielectric
> >thickness. The data bus in question is routed on S1. Power plane P is =
=3D
> >split.
> >
> >Sa
> >Dielectric thickness=3D3D 4.3
> >G
> >Dielectric thickness =3D3D 4.5
> >Sb
> >Dielectric thickness =3D3D 14.3
> >P
> >Dielectric thickness =3D3D 4.5
> >S1
> >Dielectric thickness =3D3D 13.5
> >S2
> >Dielectric thickness =3D3D 4.5
> >G
> >Dielectric thickness =3D3D 4.3
> >Sd
> >
> >I hope this helps.
> >
> >Thanks
> >Nitin
> >
> >
> >
> >
> >
> >-----Original Message-----
> >From: Doug Smith [mailto:doug@xxxxxxxxxx]=3D20
> >Sent: Monday, April 11, 2005 1:25 PM
> >To: Nitin Sood
> >Cc: si-list@xxxxxxxxxxxxx
> >Subject: Re: [SI-LIST] split plane
> >
> >Hi Nitin,
> >
> >Can you give us the vertical plane spacings/total board thickness?=3D20
> >This is necessary for a good answer.
> >
> >Doug
> >
> >Nitin Sood wrote:
> >
> > > Hello everyone,
> > >=3D20
> > > I have a synchronous data bus running at 66 MHz between FPGA and an =
=3D
> >=3D3D
> > > ASIC.
> > > The trace in question is routed on S1 while the power plane P is spli=
t =3D
> >=3D3D
> > > up.
> > > This trace traverses over the split plane in between FPGA and =3D
> >ASIC.=3D3D20
> > >=3D20
> > >=3D20
> > > S
> > > G
> > > S
> > > P
> > > S1
> > > S2
> > > G
> > > S3
> > >=3D20
> > > How can I measure the effect of the Split plane on the integrity of m=
y =3D
> >=3D3D
> > > signal
> > > on the board and what is the usual approach to this problem in such a
> > > scenario where crossing the split plane is unavoidable.=3D3D20
> > >=3D20
> > > Any suggestion would be greatly appreciated. Thank you.
> > >=3D20
> > > Regards
> > > Nitin
> > >=3D20
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>=20
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