[SI-LIST] split plane
- From: "Nitin Sood" <Nitin.Sood@xxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 11 Apr 2005 10:24:20 -0700
Hello everyone,
I have a synchronous data bus running at 66 MHz between FPGA and an =
ASIC.
The trace in question is routed on S1 while the power plane P is split =
up.
This trace traverses over the split plane in between FPGA and ASIC.=20
S
G
S
P
S1
S2
G
S3
How can I measure the effect of the Split plane on the integrity of my =
signal
on the board and what is the usual approach to this problem in such a
scenario where crossing the split plane is unavoidable.=20
Any suggestion would be greatly appreciated. Thank you.
Regards
Nitin
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