[SI-LIST] Re: split plane
- From: "Nitin Sood" <Nitin.Sood@xxxxxxx>
- To: <doug@xxxxxxxxxx>
- Date: Mon, 11 Apr 2005 13:41:18 -0700
Hi Doug,
The total board thickness is ~ 60 mills and with the following =
dielectric
thickness. The data bus in question is routed on S1. Power plane P is =
split.
S
Dielectric thickness=3D 4.3
G
Dielectric thickness =3D 4.5
S
Dielectric thickness =3D 14.3
P
Dielectric thickness =3D 4.5
S1
Dielectric thickness =3D 13.5
S2
Dielectric thickness =3D 4.5
G
Dielectric thickness =3D 4.3
S
I hope this helps.
Thanks
Nitin
-----Original Message-----
From: Doug Smith [mailto:doug@xxxxxxxxxx]=20
Sent: Monday, April 11, 2005 1:25 PM
To: Nitin Sood
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] split plane
Hi Nitin,
Can you give us the vertical plane spacings/total board thickness?=20
This is necessary for a good answer.
Doug
Nitin Sood wrote:
> Hello everyone,
>=20
> I have a synchronous data bus running at 66 MHz between FPGA and an =
=3D
> ASIC.
> The trace in question is routed on S1 while the power plane P is split =
=3D
> up.
> This trace traverses over the split plane in between FPGA and =
ASIC.=3D20
>=20
>=20
> S
> G
> S
> P
> S1
> S2
> G
> S3
>=20
> How can I measure the effect of the Split plane on the integrity of my =
=3D
> signal
> on the board and what is the usual approach to this problem in such a
> scenario where crossing the split plane is unavoidable.=3D20
>=20
> Any suggestion would be greatly appreciated. Thank you.
>=20
> Regards
> Nitin
>=20
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>=20
>=20
>=20
--=20
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