[SI-LIST] source of DDR 4 timing recommendations
- From: eric silist <ericsilist@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 1 Aug 2014 15:49:39 -0400
Can anyone help me understand the source of the pcb routing recommendations
I see for DDR4. For instance DQ to DQS timing for a byte lane? I see
some papers quoting 90ps or 50mil, but I don't know where those numbers
come from.
At a basic level I understand that DQS is the clock for the data byte on
DQ, And that the total timing budget must be spread across chip, package,
board, and dram. If I look at say DDR4-2800 that's a clock of 1.4Ghz with
a period of 714ps. So at double data rate I figure each byte is 357ps
wide. Then that should mean I have +/- 178ps of total margin that the DQS
can move from it's ideal position of being in the center of the. I think
:) Maybe that's where the 90ps for the board and 90ps for chip come from.
Anyway I'm just having trouble finding a good explanation to help me
understand how all that timing margin is calculated for each piece in the
chain.
I did try to look up DQ-DQS timing in the JEDEC standard and it just says
TBD. I've found several docs that give me an idea of what values to use,
but none so far that explain how they are calculated. I feel like this is
still an SI related question since I'll use this information to setup
constraints for my simulations but sorry if it's off topic.
Thank you.
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