[SI-LIST] Re: source of DDR 4 timing recommendations
- From: "Bhagwath, Nitin" <Nitin_Bhagwath@xxxxxxxxxx>
- To: "ericsilist@xxxxxxxxx" <ericsilist@xxxxxxxxx>, "SI-List (si-list@xxxxxxxxxxxxx)" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 15 Aug 2014 21:27:07 +0000
Hello Eric,
Keep in mind that DDR4 controllers should support DQ bit training. This means
that they should be able to delay each DQ by an amount appropriate to center it
with respect to the DQS. So you'd think that you have the whole entire UI to
mess around with ISI, Noise, and other frivolous whatnots, right?
(of course not!)
As you mentioned, the UI is divided up into the chip, package, board and DRAM.
Now, the DDR controller and DRAM industries are far more concentrated than the
PCB industry. The haggling over where the timing budget is allocated is, well,
very democratic - two wolves and a lamb vote on what's for dinner. In your
+/-178ps example, that makes me wonder about the 90ps allocated for the PCB.
90mil, maybe. (If you verify 90ps, please do pass on a link - it could be a
good controller)
Usually, since the DRAM side is fixed by JEDEC, and PCB guys having little
voice since they're dispersed and come late into the game, the PCB requirement
numbers usually come from whoever you choose as your controller. You pay mucho
$ for your controller, you're likely to get a big fat PCB timing margin (and a
free dinner from the friendly sales rep). If you're in a low cost consumer
biz, and you use the controller your boss got a sweet deal on from the guy he
met in NY who also tried to sell your boss the Brooklyn Bridge, well, there
goes your PCB timing budget along with that month for debug. Either way, you
should probably understand the capabilities and limitations of your controller
since that'll be a big variable in your PCB timing budget.
Of course, before you fab your board, you can simulate it with your favorite
simulator vendor (Mentor Graphics has a fantabulous HyperLynx DDR Wizard which
now supports DDR4) to give you that month of your life back, but you still
should know the capabilities and limitations of your controller to know whether
what you're seeing is good enough or whether the margins are too tight. Those
controller timing numbers will likely be the key to explain your PCB
requirements. If you want to know the details of why exactly the controller
eats up so much of the budget, well your getting a good answer depends on the
amount of sales you give the controller vendor.
Regards,
-Nitin
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of eric silist
Sent: Friday, August 01, 2014 12:50 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] source of DDR 4 timing recommendations
Can anyone help me understand the source of the pcb routing recommendations
I see for DDR4. For instance DQ to DQS timing for a byte lane? I see
some papers quoting 90ps or 50mil, but I don't know where those numbers come
from.
At a basic level I understand that DQS is the clock for the data byte on DQ,
And that the total timing budget must be spread across chip, package,
board, and dram. If I look at say DDR4-2800 that's a clock of 1.4Ghz with
a period of 714ps. So at double data rate I figure each byte is 357ps
wide. Then that should mean I have +/- 178ps of total margin that the DQS can
move from it's ideal position of being in the center of the. I think
:) Maybe that's where the 90ps for the board and 90ps for chip come from.
Anyway I'm just having trouble finding a good explanation to help me understand
how all that timing margin is calculated for each piece in the chain.
I did try to look up DQ-DQS timing in the JEDEC standard and it just says
TBD. I've found several docs that give me an idea of what values to use,
but none so far that explain how they are calculated. I feel like this is
still an SI related question since I'll use this information to setup
constraints for my simulations but sorry if it's off topic.
Thank you.
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