[SI-LIST] Re: hspice convergence problem
- From: "Vani Kaushik" <vanisekharan@xxxxxxxxx>
- To: leohu@xxxxxxxxxx
- Date: Mon, 21 Aug 2006 14:06:31 -0700
Hi Leo,
This questions seems so familiar to me. I had similar problems during my
hspice simulations... among modes of simulation fast used to be creating
such problems of time step.
Thought i could share my way to arriving at the simulation results :)
I tried most of the below tips to resolve the issue
1. Increase itl4, which is the # of iterations hspice will try at one
time point, before giving up and taking a smaller time step. Default =
8.
This will likely affect runtime performance.
.option itl4 = 50
itl4 = 100
2. Loosen tolerance limits from their defaults:
.option reltol=1e-3 abstol=1e-8
reltol=5e-2 abstol=1e-7
reltol=1e-2 abstol=1e-6
3. Help the circuit by adding admittance and capacitance elements
between each node and ground:
.option gshunt=1e-12 cshunt=1e-12
gshunt=1e-11 cshunt=5e-11
gshunt=1e-10 cshunt=1e-11
gshunt=1e-9 cshunt=1e-10
(Note: this is the largest value I would recommend; increasing
g,c shunt larger will reduce simulation accuracy.)
4. Increase tstep value, to step over possible model discontinuities:
.tran tstep tstop ->
.tran (2)*tstep tstop
.tran (2.5)*tstep tstop
.tran (3)*tstep tstop
5. A toggle type option that may help certain high gain, analog
(op-amp) and/or oscillitory circuits (such as an inverter ring) during
tran analysis is changing integration methods. Note the time of the
tran error with default 'trap' method, then try 'gear'. If your
simulation gets furthur into the tran run, then stick with 'gear'.
Otherwise, disable the gear option.
.option method=gear
6. If you're still having trouble with timestep too small after trying
the above steps, you should investigate the device models used. For
CMOS,
make sure you have finite terminal capacitances and resistances.
For level 49, be sure you have the model parameters below: (these are
samples, not defaults)
.model mname nmos level=49 version=3.2
+ cj=5e-4 cjsw=1e-10 cgd0=1e-10 cgs0=1e-10 rs=1e-9 rd=1e-9
In the case of BJT device, be sure to have the following model param-
eters set: (examples, not default)
.model mname npn rb=50 rc=.4 re=1e-3
7. The last scenario I have encountered is the timestep too small error
occuring at time = 0; there are typically two reasons for this. Either
dc analysis wasn't performed, or unrealistic .ic voltages have been set,
and hspice can't converge with the given node voltages. Look for the
error differences between old and new iteration value, and try setting
the
node voltage with .nodeset statement somewhere closer to new guess. In
general, .nodeset is more appropriate than .ic.
But as the gurus say most of these come at the cost of too much assumptions
on accuracy, hence will cost you the same! In my case i zeroed in on an
external resistor termination, a pull down to ground which was causing
problem.
Since, all circuits are about solving of equations, convergence is a matter
of zeroing on the right values for the variable which in transient analysis
case is also a timestep. A guess at the node voltage could always help, so
nodeset option is quite helpful, if you dont want to play with accuracy
parameters. But this requires understanding of the circuit which could be an
issue when dealing with encrypted models. Sometimes it also helps to dig on
the external termination that we apply to the models and topology as was in
my case. I would suggest that you verify the whole topology by playing
around the values of resistors or even the need for them! I am assuming that
you have done the compliance simulation or assured of the hspice models you
are using in the topology.
Hope I have helped you a lil here :)
all the very best
thanks and warm regards
Vani
On 8/21/06, Andrew Ingraham <a.ingraham@xxxxxxxx> wrote:
>
> Leo,
>
> Convergence problems are as old as SPICE itself.
>
> There are books written about SPICE that devote chapters to helping solve
> convergence problems.
>
> You need to understand ... SPICE is not an authority and there is no right
> or wrong method to using it. There are countless choices you can make
> with
> the options and all of them result in a simulation which is only an
> approximation to reality. There is no one combination that could be
> called
> "correct". (Though there may be some options that your vendor who gave
> you
> their SPICE models says you should use for their models.) Electronic
> circuit simulation is sometimes more art than science, despite decades of
> work since it was created.
>
> Some things that may or may not help:
>
> SPICE has two solution algorithms: TRAPezoidal and GEAR. Occasionally it
> helps to change to the alternate method.
>
> Making RMIN smaller probably makes SPICE more likely to get stuck. Going
> in
> the other direction may help, but eventually this affects accuracy, so try
> several values and see how it affects your results.
>
> Play with increasing the various tolerances (anything with "TOL" in the
> name), but again keep in mind that the things you do to improve
> convergence,
> tend to decrease accuracy by letting SPICE be more sloppy.
>
> If you have no luck with the other options, you can try simulating only
> portions of your netlist. Sometimes there is a bad model in there which
> is
> causing all the trouble. The trick is locating it! Often problems only
> show up when elements are combined. Also don't try simulating more than
> you
> really need to.
>
> Regards,
> Andy
>
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