[SI-LIST] Re: May I know how can I check the ibis model from vendor

  • From: "Abe (Abbas) Riazi" <ariazi@xxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Mon, 21 Aug 2006 11:50:33 -0700

 Dear Sanjay,

In order to produce reliable simulation results, It is a good idea to
evaluate the quality of an IBIS model before applying it in system
simulations.  Some steps to validate an IBIS model include:

1. Run the latest version of IBIS golden parser.
   This allows identifying several types of model deficiencies such as
   syntax errors, DC endpoints mismatches, non-monotonicities, etc.

2. Visually inspect the I-V and V-t tables using a software such as
Visual IBIS Editor.
   Check these curves to ensure they are complete and without any
glitches.  =20
   Make sure that pullup and pulldown curves have slopes which are flat
above Vcc.
   Clamp curves need to be flat above 0V.
   The model V-t data should include sufficient number of points (at
least ten)
   in the transition regions.

3. Check the Package parasitics and value of C_comp for correctness and
   reasonable values.

4. Simulate the model using basic test loads.

5. Review the IBIS Quality Checklist for quality levels 0, 1 and 2
   definitions.

   It is also useful to know ways of correcting (the identified) IBIS
model problems.

   Best Regards,

   Abe Riazi,
   ServerWorks


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of pal pal
Sent: Saturday, August 19, 2006 4:01 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: May I know how can I check the ibis model from
vendor

 Hi, We are using Micron SDRAM "MT48LC16M16/TSOP54" as a standard
peripheral for MPC8245. While executing prelayout simulations, we found
ringing and overshoots/ undershoots regardless of tracelength and
frequency; we have alsotested the same with verious series terminations.
Unfortunately all results are not acceptable. We are using the IBIS
model from the micron website. Also we have tried with the other
compatible SDRAM memory IBIS models from Samsung and Infineon. The
simulation results for pre as well as post layout are very good with the
appropriate terminations. Is this problem related of I/O mismatch or
there is any problem in IBIS model available on
website.   Thanks sanjay=20

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