[SI-LIST] effects of pattern on transmission line - DDR2
- From: "San Miguel, Shane" <shane.san.miguel@xxxxxxxxx>
- To: "silist" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 15 Jan 2004 11:31:44 -0800
I have two data patterns of interest (I'll try text) both are a 4 burst
of 4 type
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In the first pattern we have an alternating 010101 type of pattern. The
second pattern is all zero's with a 1 in the middle. The first pattern
(more traditional) is intended to stabilize the transmission line before
the measurement is made. We forget the first and last couple of edges
and make rise/fall time measurements on each of the edges in the middle
of the train.
My thinking is that the second pattern will produce a slower edge
because you have no activity and the BAM! You have to fill up all this
trace capacitance and by the time you do that, the data is done.
I guess my "rule of thumb" is what is stumping me. I look at the first
pattern and go "ok, stable DC level, more repeatable results". I look
at the second pattern and go "look at that inductive kick - what a
reflection" or "how much is that edge going to roll over"...
Anyone care to educate me on the transmission line behavior with the two
patterns?
Shane San Miguel
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