Lots of good points brought up with this thread. I agree with Al Neves that
there is lack of systematic design discipline throughout the entire process.
Just because a certain differential via geometry worked in one configuration
and for certain stack-up, bit rate, silicon technology and system architecture,
it does not mean one can blindly follow the same configuration for every
design. It's like blindly following a vendor's reference design in a completely
different board design. Do so at your own risk!
Unfortunately we cannot always build test boards every time we want to do
what-if analysis for every configuration. Instead we have to trust simulation.
And in order to trust the simulation, we must know the tool, have intuition of
what to expect with results, and correlate simulation with a good reference
design and good measurements. One way to validate the tools is to compare
against a reference platform. The CMP-28 platform is an excellent platform for
this. Once we achieve simulation correlation to measured results, we can then
have confidence in the tool and do some what-if analysis.
Yuriy time and time again has shown his Simbeor tool correlates well with
measured results. So I have no doubt in trusting his simulation results. He has
kindly spent a lot of his time putting together these great videos to help us
all visualize the electromagnetic propagation through different structures to
help us all gain the intuition.
Since many here are questioning the validity of stitching vias to mitigate
xtalk, we can take this one step further and put in some numbers. Yuriy has
shared with me the S-parameters for the three test cases, and I decided to
quickly do some transient analysis in ADS to actually measure how much near-end
and far-end crosstalk voltage was being coupled in this particular structure. I
have summarized everything in a few slides that can be found here:
https://dl.dropboxusercontent.com/u/89802638/Diff_via_XtalkTimeDomain.pdf
The numbers speak for themselves. The aggressor voltage on port (1,2) was 1V
p-p. In the first case, with 20mil separation and no stitching vias, the NEXT
was ~14% and FEXT was ~6%. When the separation was 40 mils, NEXT was 4% and
FEXT was 3.7%. When stitching vias were added, then NEXT reduced to 1.1% and
FEXT reduced to 0.8%.
DO we need stitching vias to control crosstalk? Well as usual it depends. If
your particular Serdes channel can tolerate 14% NEXT (per this via model
example), then no, you probably don't need them for X-talk control. That
doesn't mean you don't need them to mitigate differential to common conversion.
My own experience has shown that stitching via placement should be a
symmetrical distance away, with respect to their respective via, to minimize
the skew which leads to mode conversion. I.E. if one gnd via was placed 1mm
away from the positive via, the other gnd via must be 1mm away from the
negative via. If only one via is used, then it should be placed symmetrically
offset between the two. The only way to optimize placements of the stitching
vias is through simulation of your particular via geometry, antipads and
stackup.
Best regards,
Bert Simonovich
Signal/Power Integrity Practitioner | Backplane Specialist | Founder
LAMSIM Enterprises Inc.
Web Site: http://lamsimenterprises.com
Blog: http://blog.lamsimenterprises.com/
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Alfred P. Neves
Sent: 9-Dec-16 12:19 PM
To: si-list
Cc: Lee Ritchey; dmarc-noreply@xxxxxxxxxxxxx; Yuriy Shepnev; Scott McMorrow
Subject: [SI-LIST] Re: XTalk power flow in differential vias
SI-folks:
This thread speaks to what we believe is the most significant problem in signal
integrity: a lack of systematic design throughout the entire process.
Test and measurement-simulation Channel Modeling platforms play a critical role
in achieving practical signal integrity, but they are not always designed to be
“practical†or exactly mimic actual systems. They are designed to include
de-embedding, material identification, and variances in the design to capture a
full spectrum of EM behavior (example is intentionally designing a 1.85mm
connector tuned launch, excess capacitance launch, and excess inductive
launch) - the tools required for systematic design. They also should include
cross sectional analysis and a host of IPC, Beatty standard, GMS (Simbeor), and
SPP Light material identification test structures. Their key purpose is for
the SI team to achieve mastery and confidence of design using their EDA and
measurement tools.
When the EDA simulation results correspond to a spectrum of varying EM behavior
you have complete control over your high speed design methodology. A
Technology Development Platform precedes a practical product design cycle and
serves to mitigate critical risk factors inherent in EDA tool issues, making
good measurements, design methods, fabrication and material modeling.
Folks who compare the value of the two technologies and make negative
judgements on test platforms don’t understand the methodical and systematic
design effort required to achieve 40-70GHz realm stellar signal integrity, and
then they spin, spin …. more spin, and base all engineering on heuristic
rules of thumb and sheer experience of designing scores of poor to mediocre
performing systems or test platforms.
Yuriy based his tutorial on some via crosstalk coupling structures on one of
our platforms, the Serial Link XTALK-32, used for generating real crosstalk for
SERDES characterization. If anyone is interested in exploring the 2 via
systems in Simbeor send me a private mail to obtain the workspace of those
structures, along with measurements, stackup and material properties. WRT
consistently achieves VERY good correspondence between measurement and
simulation using Simbeor and are excited about the new power flow visualization
tools as another arrow in our quiver of design methods.
- Al Neves
Products for the Signal Integrity Practitioner
Alfred P. Neves
Chief Technologist
Office: 503-679-2429
www.wildrivertech.com <http://www.wildrivertech.com/>
2015 Best In Design&Test Finalist
On Dec 8, 2016, at 3:39 PM, Scott McMorrow <Scott@xxxxxxxxxxxxx> wrote:
Lee
The information I am conveying is not on test boards. It is on real, living
designs using mid board optics with measurements of the far end eyes. Same
device and connector were used by multiple companies. There were multiple
board designs, some of which did not follow stated guidelines. Others where
Teraspeed Consulting was brought in to advise on the design.
Because these are customer designs, the results cannot be shared. You'll
need to trust me on this one.
Why are optical modules an issue, as opposed to large ICs, switch chips,
FPGAs? Because optical modules typically are desgned for the lowest power,
and as a result have little equalization, and no clock recovery. There is
nothing to clean up a signal. Jitter passes right through from the electrical
domain to the optical domain and back again.
Scott
Teraspeed Consulting - A Division of Samtec Scott McMorrow, Technical
Director SI/PI Office 401-284-1827 www.teraspeed.com | www.samtec.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Lee Ritchey
Sent: Thursday, December 8, 2016 6:13 PM
To: dmarc-noreply@xxxxxxxxxxxxx; shlepnev@xxxxxxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: XTalk power flow in differential vias
I have already built dozens of test PCBs. I think the burden is on those
making the claims to show that this is a real problem with real boards rather
than visible on a test PCB.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of heyfitch ;(Redacted
sender "heyfitch" for DMARC)
Sent: Wednesday, December 7, 2016 5:26 PM
To: leeritchey <leeritchey@xxxxxxxxxxxxx>; shlepnev@xxxxxxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: XTalk power flow in differential vias
You are free to design your own test board to convince yourself one way or
another. Right?
- VadimÂ
On Wednesday, December 7, 2016, 17:01, leeritchey
<leeritchey@xxxxxxxxxxxxx>
wrote:
Cadin, I do design with hundeds of channels densely packed. Â There is no
room for "stitching vias'. Â These all work very well. Â You will find this
the norm with big iron.
Maybe stitching vias are over kill. To use them I would have to be shown that
their effect is significant rather than just visible .
Sent via the Samsung Galaxy S® 6, an AT&T 4G LTE smartphone--------
Original message --------
From: heyfitch <heyfitch@xxxxxxxxx>
Date: 12/06/2016 8:36 PM (GMT-08:00)
To: leeritchey@xxxxxxxxxxxxx, shlepnev@xxxxxxxxxxxxx,
si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: XTalk power flow in differential vias
blockquote, div.yahoo_quoted {margin-left:0 !important;border-left:1px
#715FFA solid !important;padding-left:1ex
!important;background-color:white;}Lee,In fiber optics modules, for example,
the density is so high that diff vias are often right next to one another.
 The natural inclination is to have as few stitching vias as
possible - to have more routing channels. Â So, 2 stitching vias per
a diff via is typical. Â Yuriy's video clearly shows how the lower
number of stitching vias result into higher insertion loss. Â This is
a trade off consideration, imho. Also, it is desired to have less
than 40dB crosstalk between channels. That is another consideration.Â
Regards,Vadim Heyfitch
On Monday, December 5, 2016, 13:49, Lee Ritchey
<leeritchey@xxxxxxxxxxxxx>
wrote:
Why are we worrying about differential vias?
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Yuriy Shlepnev
Sent: Monday, December 5, 2016 11:58 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] XTalk power flow in differential vias
Hello Everyone,
Last Friday I have uploaded visualization of crosstalk power flow in
differential vias - see #2016_13 at
http://www.simberian.com/ScreenCasts.php
 -> How Interconnects Work (higher quality, but may be slow), YouTube
version is available at https://youtu.be/IyuQIl8T_uE The demo video ;
illustrates two ways for the crosstalk reduction. I was really fascinated
with the power flow view of the crosstalk :-) As always, I will appreciate
any feedback.
Best regards,
Yuriy
Yuriy Shlepnev, Ph.D.
President, Simberian Inc.
2629 Townsgate Rd., Suite #235, Westlake Village, CA 91361, USA Office
+1-702-876-2882; Fax +1-702-482-7903 Cell +1-206-409-2368; Virtual
+1-408-627-7706
Skype: shlepnev
www.simberian.com
Simbeor - Accurate, Productive and Cost-Effective Electromagnetic
Signal Integrity Software 2010 and 2011 DesignVision Award Winner,
2015 Best In Design&Test Finalist
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