Hi Anto,Â
This is another very good paper from other authors devoted to the PDN voltage
noise analysis. In spite I worked very close with authors and developed some
methodologies that were used in this paper, particular for charge per cycle and
dynamic current measurements, I prefer that this paper authors will answer your
questions.
Just want to note that:1. mV/div in  Figures 10 and 11 are different.  Â
That is why it is hard to see voltage spikes in Figure 11, but they are here
(magnify the image and you will see its).Â
2. Your supposing is correct. This paper demonstrates effects that have the
same origin, as effects in Steve Sandler paper: interaction between different
system resonances.Â
Best regards,Iliya
On Thursday, May 7, 2015 2:12 AM, Anto Davis <antokdavis@xxxxxxxxx> wrote:
Hi,
I am going through the paper "On-Chip PDN Noise characterization and
Modeling", DesignCon 2010.
I have few doubts:
1. Please see the Figures 10 and 11. In Fig. 10 during switching I can see
spikes, but in Fig. 11 I don't see it.
Why is it so?
2. What is the impedance value of antiresonance peak (33 MHz)?
In a similar paper "System Power Distribution Network Theory and
Performance with Various Noise Current Stimuli Including Impacts on Chip
Level Timing", IEEE 2009 CICC, I see that the PDN used is different.
3. In Table 1, Periodic burst at 33 MHz produced more voltage than that
with the AC steady state is due to higher switching current in this case
right?
In steady state only one toggle at 33 MHz, but in periodic burst, there are
8 switchings in the time period of 33 MHz.
So, this approximately requires 8 times more switching current.
4. Does the periodic burst produce a voltage greater than, IxZ at 33 MHz?
---> Is it violating the target impedance method like the examples
discussed in the EDN article by Steve and the paper by Xiang Hu? (I guess
it is not)
Thanks,
Anto
On Fri, May 1, 2015 at 10:11 AM, Anto Davis <antokdavis@xxxxxxxxx> wrote:
Thanks Iliya,
I am going through the papers.
Anto
On Fri, May 1, 2015 at 4:17 AM, Iliya Zamek <i_zamek@xxxxxxxxx> wrote:
Anto,
I agree with Larry and Istvan comments regarding your notes on Steve
Sandler EDN paper.
This very good paper demonstrates an effect in a PDN that could not be
predicted by Target Impedance approach. The effect (rogue waves) is a worse
case voltage peak that might happen in PDN due to adding resonances
responses âin-phaseâ at special current stimulusâ frequencies and
phases.
                         Â
         This
result is expected, if we take into account that Target Impedance method is
a frequency domain approach which is dealing with steady state PDN
conditions, while voltage and current peaks are time domain phenomenon.
Consequently, to figure out correctly the voltage peaking in PDN, the
Time Domain analysis should be implemented, as Istvan noted, and Steve
did.
The Target impedance method has other serious problem: adding decoupling
capacitances on PCB in order to reduce PDN impedance, the PDN resonances,
looking from the chip die, are rising. You might find numerous measurement
confirmations of this in the literature and, particular, here:
http://www.semtech.com/power-management/On-Chip-Jitter-and-System-Power-Integrity.pdf
. Larry Smith did very good work on PDN resonances analysis in his recent
papers.
PDN Time Domain behavior could not be analyzed fully without analysis of
the on-chip transient effects. We presented this in a Tutorial we did (with
Larry and Steve Weir) at last Designcon â âSystem Power Integrityâ. You
might want to see it in the conference proceedings.
Thank you.
Iliya Zamek
 On Thursday, April 30, 2015 6:24 AM, Istvan Novak <
istvan.novak@xxxxxxxxxxx> wrote:
Anto,
I was referring to the peak distortion analysis only because that is a
familiar term for
most SI engineers. The corresponding PDN process was called Reverse
Pulse Technique
and to the best of my knowledge first appeared in the EPEP conference
proceedings:
Drabkin, et al, âAperiodic Resonant Excitation of Microprocessor power
Distribution Systems
and the Reverse Pulse Technique,â Proceedings of EPEP 2002, p. 175.
You can also look at the DesignCon2006, Santa Clara, CA, February 6-9,
2006, material
Bypass Capacitor Selection Based on Time Domain and Frequency Domain
Performances
in TecForum TF-MP3 "Comparison of Power Distribution Network Methods"
posted at http://www.electrical-integrity.com/ which also shows what
happens in case
of non-flat impedance profiles (Figures 3 through 14).
Regards,
Istvan Novak
Oracle
On 4/30/2015 2:26 AM, Anto Davis wrote:
Thanks for the inputs,Time-Domain
I found many articles on the same topic with triangular pulses, as Dr.
Istvan Novak pointed out.
Then I found this EDN article and the article "On the Bound by
Power Supply Noise Basedpulse.
On Frequency-Domain Target Impedance"Â by Xiang Hu using a different
by
I tried this case, in LTspice by writing Matlab code to generate the
current pulses as explained in the EDN ariticle.
I was able to see the maximum voltage to be higher than that predicted
the target impedance.tell
But, this limit is nothing more than the sum of InZn, where In is the
fundamental frequency of the trapezoidal waveform, which can be maximum
upto 1.3.
So the worst case PDN voltage can be directly predicted by summing these
values right?
In peak distortion analysis, are they finding out the worst case noise
current peak at a particular frequency and sum it??
I could not find the paper told by Dr. Istvan, if it is published, pls
me the title.it.
Thanks,
Anto
On Thu, Apr 30, 2015 at 1:35 AM, Smith, Larry <larrys@xxxxxxxxxxxxxxxx>
wrote:
Anto - While it is theoretically possible to establish the PDN current
waveforms that Steve Sandler has in his excellent article, it is very
difficult to do this intentionally, and extremely unlikely that it will
occur naturally in an electronic product. Xiang Hu first explored the
rogue wave concept in his PhD work at UCSD and Steve has "socialized"
switch,
Dynamic current consumption in CMOS products has its basis in charge
packets generated at the clock frequency. If the clock does not
at thedynamic current is not consumed. The charge consumption is complete
logicend of a clock cycle or else we would fail to meet setup time because
fewcircuits are still switching. (This is the general rule, there are a
currentspecific exceptions). I think this is what you are describing by "10%
triangular waveform".
The charge packets (current impulses) are integrated by the on-die
capacitance and further filtered by the package inductance so that the
current waveform in any branch of the package circuit is smoothed out.
CMOS clocks in core circuits are often several GHz and that is the
boundsimpulse rate. But the filtered current waveform that arrives in the
package has a rise time that is usually greater than a couple of nSec.
That would be the fastest current edge rate and fits well within the
theof Steve's current waveform assumptions.
There are several CMOS operations that can cause abrupt changes in PDN
current including clock gating and power gating. Current consumed by
filteredchip can easily go from essentially zero to 10's of amps in just a few
clock cycles with extreme manipulations of the clock. This transient
current arrives in the package in just a few nSec. It is further
bulkby package capacitors (if any), high frequency board capacitors and
uSec, 4capacitors before it arrives at the voltage regulator. By the time it
gets to the voltage regulator, the current rise time may be 10's of
train.orders of magnitude increased from what it was on the chip. This is
consistent with the frequency span of Steve's impedance chart. A well
designed PDN has energy (electric charge or magnetic fields) stored in
reactive elements that soften the current transient along the power
current
Microprocessors are capable of fully stimulating (modulating) the
operationswaveform down to very low frequencies, with a time period measured in
seconds. Vector processing and large matrix manipulations can do this.
Cache misses and recovery where the processor has to wait for data from
electronic or even rotating memory can do this. Power saving
frequenciescan definitely do this with clock gating effective at higher
general, theand power gating (completely cycling the power on and off) at lower
frequencies with periods on the order of 1 uSec or longer. In
at anyPDN may be called upon to deliver current transients of 10's of amps
ofsub-harmonic of the clock. But this is often mitigated by hardware,
firmware or software techniques to make things easier on the PDN.
So the answer to your question is yes, there are ICs that are capable
isdrawing these types of waveforms.
While the rogue wave concept is intriguing and compelling, it will not
occur with a well-designed PDN. For economic reasons we often have one
resonant peak with a q-factor of 3 or higher. But if the PDN designer
impedancedoing his/her job, we should never have multiple high q-factor
wavepeaks. This as well as a highly improbable string of current pulses at
exactly the right frequency and phase are required to make the rogue
si-list-bounce@xxxxxxxxxxxxx]happen.
Regards,
Larry Smith
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:
trapezoidalOn Behalf Of Anto Davis
Sent: Wednesday, April 29, 2015 7:14 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Why is the excitation pattern sharp edged
http://www.edn.com/design/test-and-measurement/4413192/3/Target-impedance-based-solutions-for-PDN-may-not-provide-a-realistic-assessmentinstead of a 10% triangular
Hi,
I have a doubt,
Please look at the link below:
ednTargetImpedance
<
insteadWhy is the switching excitation pattern a sharp edged trapezoidal
randomized it.of a 10% triangular waveform at some processor frequency?
At least it should have been modulated with this pattern, or
be
Say because of the microprocessor operations, lower frequencies are
excited, it will look like a modulated wave.
But in this case also, the amplitude of lower frequency currents will
Current-very small right?
Is there any entity in an IC draws this type of current waveforms?
I have a related doubt, what is the nature of current taken by a
Mode differential signaling driver? Is it constant in all the time it
operates?
Thanks,
Anto
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