[SI-LIST] Re: Why is the excitation pattern sharp edged trapezoidal instead of a 10% triangular

  • From: Anto Davis <antokdavis@xxxxxxxxx>
  • To: "Smith, Larry" <larrys@xxxxxxxxxxxxxxxx>
  • Date: Fri, 8 May 2015 10:56:41 +0530

Thanks all,

"About why there are no spikes seen in Figure 11".

I have something in mind, it might be wrong, but I am writing it:

In Figure 11, we have already crossed the maximum allowed voltage margin of
the IC.
In a 1.1V logic, If we have 0.577/2 voltage dip, will the toggle flip flops
flip?
The probability of going to metastability will be higher in this case?
So in that case, instead of switching current will there be a constant
power draw?

In Figure 11, there are some places we have switching.
I think, at that location the T flip flops are toggling, and other
locations they may are not toggling.
But, here also, some phase shift is visible between the two.
If figure 19 (a) and 11 are same, I think, in Figure 11 the voltage and
switching patterns are 90 degrees phase shifted.


Another question I had was, what will happen if the IC voltage goes above
or below the +/-5%?


Thanks,
Anto





On Fri, May 8, 2015 at 4:04 AM, Smith, Larry <larrys@xxxxxxxxxxxxxxxx>
wrote:

Anto – Thanks for your interest in the papers and work that was done
several years ago at Altera. While many of the authors have moved on to
other endeavors, the subject matter is still relevant and important in the
field of power integrity. The measured waveforms and the concepts
presented in the papers are correct but some of the terminology probably
needs a little updating.



Figure 10 is called a “burst transient pattern” but I think a better name
for it would be “step response.” The clock was abruptly turned on and the
chip began drawing a transient current which caused the PDN have an
associated voltage droop. Sometime later the clock was abruptly turned off
after the system had come to equilibrium and then the PDN experienced a
voltage spike. This is the expected transient response to a square pulse
of load current with a duration much longer than the period of the PDN
resonant frequency. As discussed earlier on this thread, the spikey
impulse currents on-die have been filtered by the on-die capacitance and
package inductance so that the current waveform is smoothed out by the time
it reaches the package.



Figure 11 is called “periodic burst at PDN resonant frequency” but I think
it would have been better to simply call it the “resonance response.” It
is an AC steady state waveform, which means that the transients have died
out long ago. The PDN voltage waveform is due to the transient current of
figure 10 but now it repeats. The current steps have been turned on and
off many times at the PDN resonant frequency so we now consider this to be
the AC steady state response to a square wave of dynamic current. The PDN
waveform has re-centered itself at approximately the nominal Vdd voltage
minus DC IR drop.



Your first comment is that we see voltage spikes (clock edge noise) in
figure 10 but do not see them in figure 11. That is a good observation.
Illiya has pointed out that we are on a different scale factor. But it
still seems like we should have seen some clock edge noise in the resonance
response. The measured scope shot and simulation down in figure 19 show
the clock edge noise at the expected time. I don’t really know why the
clock edge noise did not show up in figure 11. Unfortunately, the setup is
no longer available to investigate.



To address your second comment, the impedance peak is shown in figure 4.
We did not put a marker on it but it appears to be about 60 or 70 mOhms.
The designCon paper and CICC paper show the very same time measurements (in
fact, the same scope shots) so it was the same impedance peak. We did not
show the impedance peak in the CICC paper.



You are correct about the table 1 currents. The 33 MHz clock measurement
is only drawing a small fraction of the current that was drawn when the 533
MHz clock was modulated on and off at the 33 MHz PDN resonant frequency.
Ignoring leakage current, the unmodulated current is about 15 times higher
in the 533 MHz clock case (533/33). This is the stimulus current that was
modulated for the resonance response.



For the voltage calculation in item 4, we have to be a little bit
careful. We have to use peak-to-peak currents when calculating p-p
voltage. Or, use amplitude currents when calculating amplitude voltages.
This is for the AC steady state calculations which are being assumed when
we say V=IxZ. Also, this is a square wave of current and we are filtering
out the 1st harmonic of the square wave with the PDN resonant peak. This
puts and additional factor of 4/pi (Fourier coefficient for 1st harmonic)
into the voltage calculation.



“Violating target impedance method?” There is nothing to violate. The
target impedance is simply a reference line to use when designing or
evaluating a PDN. In these two papers, there was just one PDN resonant
peak that happened to badly exceed the target impedance. The measured data
is a dramatic example of what can happen when the PDN impedance peak far
exceeds the target impedance. If the PDN impedance had met the target
impedance, or if we had limited the transient current so that the existing
impedance peak met the reduced-transient-current target impedance, the
voltage waveforms would have been well behaved. Neither the step or
resonance responses would have come close to exceeding the voltage
tolerance. As mentioned before, the rogue wave phenomenon involves
pathological stimulation of multiple impedance peaks.



Regards,

Larry Smith







*From:* Iliya Zamek [mailto:i_zamek@xxxxxxxxx]
*Sent:* Thursday, May 07, 2015 10:37 AM
*To:* antokdavis@xxxxxxxxx
*Cc:* si-list@xxxxxxxxxxxxx; Hu, Xiang; istvan.novak@xxxxxxxxxxx; Smith,
Larry
*Subject:* Re: [SI-LIST] Re: Why is the excitation pattern sharp edged
trapezoidal instead of a 10% triangular



Hi Anto,



This is another very good paper from other authors devoted to the PDN
voltage noise analysis.

In spite I worked very close with authors and developed some methodologies
that were used in this paper, particular for charge per cycle and dynamic
current measurements, I prefer that this paper authors will answer your
questions.



Just want to note that:

1. mV/div in Figures 10 and 11 are different.

That is why it is hard to see voltage spikes in Figure 11, but they are
here (magnify the image and you will see its).



2. Your supposing is correct. This paper demonstrates effects that have
the same origin, as effects in Steve Sandler paper: interaction between
different system resonances.



Best regards,

Iliya





On Thursday, May 7, 2015 2:12 AM, Anto Davis <antokdavis@xxxxxxxxx> wrote:



Hi,
I am going through the paper "On-Chip PDN Noise characterization and
Modeling", DesignCon 2010.
I have few doubts:

1. Please see the Figures 10 and 11. In Fig. 10 during switching I can see
spikes, but in Fig. 11 I don't see it.
Why is it so?

2. What is the impedance value of antiresonance peak (33 MHz)?
In a similar paper "System Power Distribution Network Theory and
Performance with Various Noise Current Stimuli Including Impacts on Chip
Level Timing", IEEE 2009 CICC, I see that the PDN used is different.

3. In Table 1, Periodic burst at 33 MHz produced more voltage than that
with the AC steady state is due to higher switching current in this case
right?
In steady state only one toggle at 33 MHz, but in periodic burst, there are
8 switchings in the time period of 33 MHz.
So, this approximately requires 8 times more switching current.

4. Does the periodic burst produce a voltage greater than, IxZ at 33 MHz?
---> Is it violating the target impedance method like the examples
discussed in the EDN article by Steve and the paper by Xiang Hu? (I guess
it is not)


Thanks,
Anto



On Fri, May 1, 2015 at 10:11 AM, Anto Davis <antokdavis@xxxxxxxxx> wrote:

Thanks Iliya,

I am going through the papers.

Anto



On Fri, May 1, 2015 at 4:17 AM, Iliya Zamek <i_zamek@xxxxxxxxx> wrote:

Anto,
I agree with Larry and Istvan comments regarding your notes on Steve
Sandler EDN paper.

This very good paper demonstrates an effect in a PDN that could not be
predicted by Target Impedance approach. The effect (rogue waves) is a
worse
case voltage peak that might happen in PDN due to adding resonances
responses ‘in-phase’ at special current stimulus’ frequencies and
phases.

This
result is expected, if we take into account that Target Impedance
method is
a frequency domain approach which is dealing with steady state PDN
conditions, while voltage and current peaks are time domain phenomenon.

Consequently, to figure out correctly the voltage peaking in PDN, the
Time Domain analysis should be implemented, as Istvan noted, and Steve
did.

The Target impedance method has other serious problem: adding decoupling
capacitances on PCB in order to reduce PDN impedance, the PDN
resonances,
looking from the chip die, are rising. You might find numerous
measurement
confirmations of this in the literature and, particular, here:

http://www.semtech.com/power-management/On-Chip-Jitter-and-System-Power-Integrity.pdf
. Larry Smith did very good work on PDN resonances analysis in his
recent
papers.

PDN Time Domain behavior could not be analyzed fully without analysis of
the on-chip transient effects. We presented this in a Tutorial we did
(with
Larry and Steve Weir) at last Designcon – “System Power Integrity”.
You
might want to see it in the conference proceedings.

Thank you.
Iliya Zamek




On Thursday, April 30, 2015 6:24 AM, Istvan Novak <
istvan.novak@xxxxxxxxxxx> wrote:


Anto,

I was referring to the peak distortion analysis only because that is a
familiar term for
most SI engineers. The corresponding PDN process was called Reverse
Pulse Technique
and to the best of my knowledge first appeared in the EPEP conference
proceedings:

Drabkin, et al, “Aperiodic Resonant Excitation of Microprocessor power
Distribution Systems
and the Reverse Pulse Technique,” Proceedings of EPEP 2002, p. 175.

You can also look at the DesignCon2006, Santa Clara, CA, February 6-9,
2006, material

Bypass Capacitor Selection Based on Time Domain and Frequency Domain
Performances
in TecForum TF-MP3 "Comparison of Power Distribution Network Methods"

posted at http://www.electrical-integrity.com/ which also shows what
happens in case
of non-flat impedance profiles (Figures 3 through 14).


Regards,
Istvan Novak
Oracle



On 4/30/2015 2:26 AM, Anto Davis wrote:
Thanks for the inputs,
I found many articles on the same topic with triangular pulses, as Dr.
Istvan Novak pointed out.
Then I found this EDN article and the article "On the Bound by
Time-Domain
Power Supply Noise Based
On Frequency-Domain Target Impedance" by Xiang Hu using a different
pulse.

I tried this case, in LTspice by writing Matlab code to generate the
current pulses as explained in the EDN ariticle.
I was able to see the maximum voltage to be higher than that predicted
by
the target impedance.

But, this limit is nothing more than the sum of InZn, where In is the
fundamental frequency of the trapezoidal waveform, which can be
maximum
upto 1.3.

So the worst case PDN voltage can be directly predicted by summing
these
values right?

In peak distortion analysis, are they finding out the worst case noise
current peak at a particular frequency and sum it??

I could not find the paper told by Dr. Istvan, if it is published, pls
tell
me the title.


Thanks,
Anto



On Thu, Apr 30, 2015 at 1:35 AM, Smith, Larry <
larrys@xxxxxxxxxxxxxxxx>
wrote:

Anto - While it is theoretically possible to establish the PDN
current
waveforms that Steve Sandler has in his excellent article, it is very
difficult to do this intentionally, and extremely unlikely that it
will
occur naturally in an electronic product. Xiang Hu first explored
the
rogue wave concept in his PhD work at UCSD and Steve has "socialized"
it.

Dynamic current consumption in CMOS products has its basis in charge
packets generated at the clock frequency. If the clock does not
switch,
dynamic current is not consumed. The charge consumption is complete
at the
end of a clock cycle or else we would fail to meet setup time because
logic
circuits are still switching. (This is the general rule, there are a
few
specific exceptions). I think this is what you are describing by
"10%
triangular waveform".

The charge packets (current impulses) are integrated by the on-die
capacitance and further filtered by the package inductance so that
the
current waveform in any branch of the package circuit is smoothed
out.
CMOS clocks in core circuits are often several GHz and that is the
current
impulse rate. But the filtered current waveform that arrives in the
package has a rise time that is usually greater than a couple of
nSec.
That would be the fastest current edge rate and fits well within the
bounds
of Steve's current waveform assumptions.

There are several CMOS operations that can cause abrupt changes in
PDN
current including clock gating and power gating. Current consumed by
the
chip can easily go from essentially zero to 10's of amps in just a
few
clock cycles with extreme manipulations of the clock. This transient
current arrives in the package in just a few nSec. It is further
filtered
by package capacitors (if any), high frequency board capacitors and
bulk
capacitors before it arrives at the voltage regulator. By the time
it
gets to the voltage regulator, the current rise time may be 10's of
uSec, 4
orders of magnitude increased from what it was on the chip. This is
consistent with the frequency span of Steve's impedance chart. A
well
designed PDN has energy (electric charge or magnetic fields) stored
in
reactive elements that soften the current transient along the power
train.

Microprocessors are capable of fully stimulating (modulating) the
current
waveform down to very low frequencies, with a time period measured in
seconds. Vector processing and large matrix manipulations can do
this.
Cache misses and recovery where the processor has to wait for data
from
electronic or even rotating memory can do this. Power saving
operations
can definitely do this with clock gating effective at higher
frequencies
and power gating (completely cycling the power on and off) at lower
frequencies with periods on the order of 1 uSec or longer. In
general, the
PDN may be called upon to deliver current transients of 10's of amps
at any
sub-harmonic of the clock. But this is often mitigated by hardware,
firmware or software techniques to make things easier on the PDN.

So the answer to your question is yes, there are ICs that are capable
of
drawing these types of waveforms.

While the rogue wave concept is intriguing and compelling, it will
not
occur with a well-designed PDN. For economic reasons we often have
one
resonant peak with a q-factor of 3 or higher. But if the PDN
designer
is
doing his/her job, we should never have multiple high q-factor
impedance
peaks. This as well as a highly improbable string of current pulses
at
exactly the right frequency and phase are required to make the rogue
wave
happen.

Regards,
Larry Smith

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:
si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Anto Davis
Sent: Wednesday, April 29, 2015 7:14 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Why is the excitation pattern sharp edged
trapezoidal
instead of a 10% triangular

Hi,
I have a doubt,

Please look at the link below:
ednTargetImpedance
<


http://www.edn.com/design/test-and-measurement/4413192/3/Target-impedance-based-solutions-for-PDN-may-not-provide-a-realistic-assessment
Why is the switching excitation pattern a sharp edged trapezoidal
instead
of a 10% triangular waveform at some processor frequency?

At least it should have been modulated with this pattern, or
randomized it.

Say because of the microprocessor operations, lower frequencies are
excited, it will look like a modulated wave.
But in this case also, the amplitude of lower frequency currents will
be
very small right?

Is there any entity in an IC draws this type of current waveforms?

I have a related doubt, what is the nature of current taken by a
Current-
Mode differential signaling driver? Is it constant in all the time it
operates?


Thanks,
Anto


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