Thanks for the inputs,
I found many articles on the same topic with triangular pulses, as Dr.
Istvan Novak pointed out.
Then I found this EDN article and the article "On the Bound by Time-Domain
Power Supply Noise Based
On Frequency-Domain Target Impedance" by Xiang Hu using a different pulse.
I tried this case, in LTspice by writing Matlab code to generate the
current pulses as explained in the EDN ariticle.
I was able to see the maximum voltage to be higher than that predicted by
the target impedance.
But, this limit is nothing more than the sum of InZn, where In is the
fundamental frequency of the trapezoidal waveform, which can be maximum
upto 1.3.
So the worst case PDN voltage can be directly predicted by summing these
values right?
In peak distortion analysis, are they finding out the worst case noise
current peak at a particular frequency and sum it??
I could not find the paper told by Dr. Istvan, if it is published, pls tell
me the title.
Thanks,
Anto
On Thu, Apr 30, 2015 at 1:35 AM, Smith, Larry <larrys@xxxxxxxxxxxxxxxx>
wrote:
Anto - While it is theoretically possible to establish the PDN current
waveforms that Steve Sandler has in his excellent article, it is very
difficult to do this intentionally, and extremely unlikely that it will
occur naturally in an electronic product. Xiang Hu first explored the
rogue wave concept in his PhD work at UCSD and Steve has "socialized" it.
Dynamic current consumption in CMOS products has its basis in charge
packets generated at the clock frequency. If the clock does not switch,
dynamic current is not consumed. The charge consumption is complete at the
end of a clock cycle or else we would fail to meet setup time because logic
circuits are still switching. (This is the general rule, there are a few
specific exceptions). I think this is what you are describing by "10%
triangular waveform".
The charge packets (current impulses) are integrated by the on-die
capacitance and further filtered by the package inductance so that the
current waveform in any branch of the package circuit is smoothed out.
CMOS clocks in core circuits are often several GHz and that is the current
impulse rate. But the filtered current waveform that arrives in the
package has a rise time that is usually greater than a couple of nSec.
That would be the fastest current edge rate and fits well within the bounds
of Steve's current waveform assumptions.
There are several CMOS operations that can cause abrupt changes in PDN
current including clock gating and power gating. Current consumed by the
chip can easily go from essentially zero to 10's of amps in just a few
clock cycles with extreme manipulations of the clock. This transient
current arrives in the package in just a few nSec. It is further filtered
by package capacitors (if any), high frequency board capacitors and bulk
capacitors before it arrives at the voltage regulator. By the time it
gets to the voltage regulator, the current rise time may be 10's of uSec, 4
orders of magnitude increased from what it was on the chip. This is
consistent with the frequency span of Steve's impedance chart. A well
designed PDN has energy (electric charge or magnetic fields) stored in
reactive elements that soften the current transient along the power train.
Microprocessors are capable of fully stimulating (modulating) the current
waveform down to very low frequencies, with a time period measured in
seconds. Vector processing and large matrix manipulations can do this.
Cache misses and recovery where the processor has to wait for data from
electronic or even rotating memory can do this. Power saving operations
can definitely do this with clock gating effective at higher frequencies
and power gating (completely cycling the power on and off) at lower
frequencies with periods on the order of 1 uSec or longer. In general, the
PDN may be called upon to deliver current transients of 10's of amps at any
sub-harmonic of the clock. But this is often mitigated by hardware,
firmware or software techniques to make things easier on the PDN.
So the answer to your question is yes, there are ICs that are capable of
drawing these types of waveforms.
While the rogue wave concept is intriguing and compelling, it will not
occur with a well-designed PDN. For economic reasons we often have one
resonant peak with a q-factor of 3 or higher. But if the PDN designer is
doing his/her job, we should never have multiple high q-factor impedance
peaks. This as well as a highly improbable string of current pulses at
exactly the right frequency and phase are required to make the rogue wave
happen.
Regards,
Larry Smith
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Anto Davis
Sent: Wednesday, April 29, 2015 7:14 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Why is the excitation pattern sharp edged trapezoidal
instead of a 10% triangular
Hi,
I have a doubt,
Please look at the link below:
ednTargetImpedance
<
http://www.edn.com/design/test-and-measurement/4413192/3/Target-impedance-based-solutions-for-PDN-may-not-provide-a-realistic-assessment
Why is the switching excitation pattern a sharp edged trapezoidal instead
of a 10% triangular waveform at some processor frequency?
At least it should have been modulated with this pattern, or randomized it.
Say because of the microprocessor operations, lower frequencies are
excited, it will look like a modulated wave.
But in this case also, the amplitude of lower frequency currents will be
very small right?
Is there any entity in an IC draws this type of current waveforms?
I have a related doubt, what is the nature of current taken by a Current-
Mode differential signaling driver? Is it constant in all the time it
operates?
Thanks,
Anto
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