Hi Sherman:
Thanks for your share, yes, it is a interesting topic, would you mind
to share some public papers on this topic?
The understand of this question may help to solve the decap estimate
request, as the power Integrity engineer often grilled by management
teamï¼How much decap on die we should add?
Most of time , we will use the Chip Level IR analysis to evaluate the
decap value/location locally.
Sometimes , people will use the System Level Impedance Analysis to get
the minimum total decaps value , a example is :
Youngwoo Kim ; Heegon Kim ; Jonghyun Cho .etc, ' Mobile AP GPU power
distribution network simulation and analysis based on chip power model '
,2016 IEEE International Symposium on Electromagnetic Compatibility
(EMC),DOI: 10.1109/ISEMC.2016.7571668
But I haven't found any documents to discuss this topic until now.
Only some relate topic is , the effective voltage drop, timing impact
with the noise integral, not the drop and the di/dt analysis.
Regards,
Robbie
Sherman Shan <shan@xxxxxxxxxx> äº2019å¹´12æ4æ¥å¨ä¸ ä¸å9:44åéï¼
Hi Robbie,
This is a very good question. Here is my thinking on it:
1. the supply range used in STA/DTA should be from the spec of the Si
process technology which can be fairly large, say +-15%;
2. for a good PI design, the system level supply range should align with
the
timing analysis supply range. A gap here is probably the system level
analysis often ends at the c4 bump which is not yet the power rail at each
IP/functional block. Regarding how to reconcile the two ranges, there are
different approaches. We can talk about it more if interested.
Regards,
Sherman Shan Chen
SI/PI Group, Kandou Bus
5 Queensbridge, Northampton, UK, NN4 7BF
Office: +44 1604 635826 Email: shan@xxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On
Behalf
Of Luping Liu
Sent: Thursday, November 28, 2019 3:10 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Why 5% Noise Specific for PDN Analysis
Hello Everyone:
Happy holiday.
A simple question confused me a long time: Why most PDN analysis use
the
5% as the noise/ripple specific? Especially on the VDD core rail.
Maybe we can see a 30mV noise specific for a 1.0V rail ,e.g. 3% , but
still the same question: Why 3% specificationé?
There should be two power integrity flow in a chip design é?
One is the system level analysis , with the Cdie/Rdie model for the full
chip. The noise ripple spec normally is 3%~5%.
Another is the chip level static or dynamic IR analysis, which should
focus on each MOS level device. The noise spec normally is 10%~15%.
The chip timing analysis should use the second one as the worst case
voltage noise, e.g. 10%~15%
So I can understand the full chip IR noise spec comes from the timing
analysis, but where the system level ripple spec comes from ?
Regards,
Robbie
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