Hi Shao Peng:
Thanks for your reply , yes, this 3% and 5% separation should be true
in the analog IPs or other hard PHYs.
If we step further to the VDD core , especially in a large die, like
FPGA or switch chip, few hundreds Amps current , while we run the Chip
Level Power Integrity Analysis using the Redhawk or Voltus tool from
Ansys/Cadence, it focuses on on-die static/dynamic IR analysis, where a
voltage source is define at the chip bumps (or BGA balls if you include the
substrate) and current sinks are applied at different nodes based on power
computed for each standard cell, to find out the voltage drop at each of
the standard cell instance in the design.
Normally , you may have up to 15% or even worse, 20% voltage drop in
dynamic IR analysis , as Sherman said, in current large chip.
Then we know the voltage source you add at bump here, is not a
perfect voltage source in real system, it should have noise or ripple too.
So, you will run a System Level Impedance Analysis here, the noise
limit you set here, possibly will be 5%, and the probe point is the bump
too.
The question is , you can't simply add this 5% with the 15% chip level
IR result , to get the worst case voltage drop result.
The reason based on my understand is , the system level impedance
analysis is based on the merged system level current profile, it is global
phenomenon, the chip level power integrity analysis use VCD or vector less
to calculate the full chip power, but focus on the localize noise, e.g.
Global noise vs Localize noise, can't simply add them together.
Regards,
Robbie
Shao Peng <doltbird1972@xxxxxxxxxxx> äº2019å¹´12æ3æ¥å¨äº
ä¸å5:16åéï¼
Hi, Luping,
I am tring to answer your question based on my experience,
chip-package-system co-simulation for switch chip.
Both 3% and 5% constrain are from the timing simulation. On package level,
we defined a 5% spec, which is the interface between the board-level and
package-level power quality. After the power distribution, we will have the
3% constrain for the chip-level power quality, to the core of memory block
or the serdes block.
If a chip is designed for commercial customer, the number (5% and 3%) is a
traditional and trade-off result. Or if you have enough confidence on your
package level power filter, you can give more room for your chip customer.
Like some chip vendors just claim how many and what type of Capacitor
needed around the chip on board.
If the chip and the system are both in-house design, then you will have
the freedom to define a new number to replace the 5% infterface between
chip and system implementation. But very few to re-define the 3%
requirement for chip, since many IP was designed by 3% margin.
Hope these helpful!
Shao Peng
System Architect and SI Consultant
________________________________________
å件人: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> 代表
Luping Liu <liewluping@xxxxxxxxx>
åéæ¶é´: 2019å¹´11æ28æ¥ 23:10
æ¶ä»¶äºº: si-list@xxxxxxxxxxxxx
主é¢: [SI-LIST] Why 5% Noise Specific for PDN Analysis
Hello Everyone:
Happy holiday.
A simple question confused me a long time: Why most PDN analysis use
the 5% as the noise/ripple specific? Especially on the VDD core rail.
Maybe we can see a 30mV noise specific for a 1.0V rail ,e.g. 3% , but
still the same question: Why 3% specificationï¼
There should be two power integrity flow in a chip design ï¼
One is the system level analysis , with the Cdie/Rdie model for the full
chip. The noise ripple spec normally is 3%~5%.
Another is the chip level static or dynamic IR analysis, which should
focus on each MOS level device. The noise spec normally is 10%~15%.
The chip timing analysis should use the second one as the worst case
voltage noise, e.g. 10%~15%
So I can understand the full chip IR noise spec comes from the timing
analysis, but where the system level ripple spec comes from ?
Regards,
Robbie
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