[SI-LIST] Re: Vias in LPDDR2 traces
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 27 Feb 2015 19:15:09 +0100
Hello,
sorry for late response, but I was on embedded world exhibition ..
I have seen so many designs leghtmatched to death because of the lentgth
matching according to strict design guides...
And this seems a similar case. If my system is that bad that I can only
allow 10ps flight time mismatch I have to search somewhere else for
trouble ..but not at the lengthe matching ..
LPDDR2 can be more critical due to the missing termination that kills
quite a bit of margin .. but still there should be still enough room in
your timing budget to allow more mismatch.
The nice thing on length mitsmatch is, that you know quite exact the
error you are making .. with a lot of meanders generating X-talk and
unknown delays (if too small serpentining is used) its much more
difficult to assess the risk ...
Nevertheless I do account for Vias and speed on different layers where
I'm involved in a Design ...
For electrical length matching:
I use the different speed at the different layers for delay calculation
(not just 10% difference, but numbers based on my material and my
stackup..) .
For a via i try to adjust the stackup/routing layers to use the full via
(so not from L2 to L3, but always from the upper half of the PCB to the
lower). This will introduce more delay, but using a the longer part of a
via without leaving a stub is preferred).
For full vias I use a rule of thumb fo 10ps /mm via length. so for the
via from L2 to L3 you are most likely not adding a real delay, but you
are concerned about the stub (but also not really at LPDDR2 speeds..)
So my conclusion is you should worry mor about the meanders that you
have in the design, the via stubst and the impdeance mismatches if you
route inside one byte on different layers.
The via delay is something you can calculate in the timing budged if you
are really concerned ...
So I ask everybody to use engineering judgement instead of following the
length matching design guides ..
Best regards
Hermann
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Am 24.02.2015 um 22:10 schrieb Jonathan Riley:
> Hi
> Please can someone provide a little advice regarding vias in LPDDR2 traces?
>
> The issue concerns the requirement to match the signal flight times to
> +/-10ps within each byte group. As a rough approximation, on my PCB this
> equates to a distance of about 1.8mm for microstrip traces or about 1.4mm
> for stripline traces. When a via is encountered, it too has length - the
> problem is how to count the via length.
>
> To illustrate what I mean, suppose a trace is routed on the top of the PCB
> but a via takes the signal down to the 3rd layer. The depth is only 0.1mm
> between these layers, but the via is a total of 1.6mm long. Suppose also
> that the impedance of the traces and also of the via are the same (40
> Ohms), then half the signal exits the via and propagates down the trace on
> layer 3, the other half goes to the end of the via and reflects back. After
> the 1.5mm down and back (equivalent to 3.0mm) the reflection reaches the
> 3rd layer and adds in another 50% of the reflected signal. But this looks
> as though it was routed with a 3.0mm longer trace. This violates the total
> length budget.
>
> While one solution is to back-drill the vias, this isn't a low-cost PCB
> solution. So what is the best way to ensure compliance with the 10ps skew
> requirement?
>
> One other question, though perhaps not a pure SI one: for most memories the
> data bits within each byte lane may be freely swapped with each other, also
> byte lanes may also be swapped with other byte lanes. So why is LPDDR2 the
> exception and such bit and byte swapping is prohibited? Are the byte lanes
> used in some manner to configure the device rather like the address bus is,
> or is there some other reason?
>
> Many thanks.
> Jon
>
>
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