[SI-LIST] Vias in LPDDR2 traces
- From: Jonathan Riley <jonathan.lloyd.riley@xxxxxxxxx>
- To: si-list <si-list@xxxxxxxxxxxxx>
- Date: Tue, 24 Feb 2015 21:10:36 +0000
Hi
Please can someone provide a little advice regarding vias in LPDDR2 traces?
The issue concerns the requirement to match the signal flight times to
+/-10ps within each byte group. As a rough approximation, on my PCB this
equates to a distance of about 1.8mm for microstrip traces or about 1.4mm
for stripline traces. When a via is encountered, it too has length - the
problem is how to count the via length.
To illustrate what I mean, suppose a trace is routed on the top of the PCB
but a via takes the signal down to the 3rd layer. The depth is only 0.1mm
between these layers, but the via is a total of 1.6mm long. Suppose also
that the impedance of the traces and also of the via are the same (40
Ohms), then half the signal exits the via and propagates down the trace on
layer 3, the other half goes to the end of the via and reflects back. After
the 1.5mm down and back (equivalent to 3.0mm) the reflection reaches the
3rd layer and adds in another 50% of the reflected signal. But this looks
as though it was routed with a 3.0mm longer trace. This violates the total
length budget.
While one solution is to back-drill the vias, this isn't a low-cost PCB
solution. So what is the best way to ensure compliance with the 10ps skew
requirement?
One other question, though perhaps not a pure SI one: for most memories the
data bits within each byte lane may be freely swapped with each other, also
byte lanes may also be swapped with other byte lanes. So why is LPDDR2 the
exception and such bit and byte swapping is prohibited? Are the byte lanes
used in some manner to configure the device rather like the address bus is,
or is there some other reason?
Many thanks.
Jon
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