[SI-LIST] Re: Tightly coupled VS loosely coupled diff pairs
- From: MikonCons@xxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 10 Sep 2001 18:29:54 EDT
Hi, Lee. I have added this response to the SI list to perhaps hear of others
experiences on the topic.
****
You asked, "Do you have some analytical evidence that tight coupling is
better? All of the analysis I have done shows that tight coupling actually
reduces signal quality, specifically edge rate and jitter.
This becomes prominent at 2.5 GB/S.
I'd be interested in some analysis that shows what the benefir of tight
coupling is."
****
I have been on the road for the last month, and will continue to be so for at
least four more weeks; therefore, my comments are brief. The abrupt answer to
your inquiry is "Yes, absolutely." A longer answer follows.
For the last three years, I have redesigned non-functional, loosely-coupled
designs, and designed multiple original, tightly-coupled designs (both
backplanes and line cards) for new, upcoming 3G systems for multiple
companies, including Nokia and CacheFlow. I am dealing with 50 ps rise times
and 2.5 to 5 GBPS systems.
As I'm sure you are aware, edge rate degradation for any line configuration
is partially dependent on the losses of the harmonics of the fundamental.
That degradation is universal and must be dealt with in all designs. However,
a potentially greater impact on edge rate occurs because of different delays
of the signal propagation on each of the two traces of a differential pair.
The edge rate degradation is 1/2 the difference in propagation delays
(originating from whatever source). Closer routing (and therefore tighter
coupling) of traces minimizes this delta in two ways; viz, minimization of
physical length differences and different effective dielectric values caused
by localized glass-resin variations in the core and pre-preg layups. More
tightly coupled traces minimize both effects. Note that the localized
variations in effective dielectric constant are near impossible to model,
even for one board vendor with a known material source and a given stackup.
These variations will vary from board to board even within one lot.
Another major contributor in edge rate degradation is non-symmetrical
coupling to adajent signal traces and pins in connector pin fields. Contrary
to recommendations made by another well-known consultant for AMP HS-3
connectors, I have conclusively demonstrated superior eye diagram performance
of pairs that bracket the signal pin rows, as opposed to the ground pin rows.
This comment is particularly applicable to CML designs (like for Vitesse
parts) as opposed to complimentary, but single-ended, drivers (like the IBM
DASL line). This degradation effect can also be encountered when dual
stripline construction includes short parallel segments near the trace pair,
but on the adjacent layer.
Still two other (perhaps obvious to you, but not to many SI analysists)
degradation mechanisms are encountered because of assymmetrical rise and fall
times of complimentary outputs, and different clock-to-output delays (skew)
of the complimentary driver outputs.
And, yes, I have modeled and analytically correlated ALL of the above effects
with real hardware designs. Most of these analyses were performed and are
parts of proprietary, cutting-edge reports to my clients; therefore, I have
not publicly published my findings for consumption by the SI community. As I
TRY to back off from a busy consulting schedule, I plan to update and expand
my own earlier seminar and publish two or three papers on this subject.
Respectfully,
Mike
Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
(408)727-5697
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